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VLSI Design, International Conference on

Jan. 4 2008 to Jan. 8 2008

Hyderabad, India

ISSN: 1063-9667

ISBN: 0-7695-3083-4

Table of Contents

21st International Conference on VLSI Design - CopyrightFreely available from IEEE.pp. iv-iv
VLSI Design Conference HistoryFreely available from IEEE.pp. xxxvi-xxxvi
Plenary Invited Keynote SpeakersFull-text access may be available. Sign in or learn about subscription options.pp. xxxviii-xxxix
Energy-Efficient Soft-Error Protection Using Operand Encoding and Operation BypassFull-text access may be available. Sign in or learn about subscription options.pp. 45-51
by Kaushal R. Gandhi, Nihar R. Mahapatra
Multimedia Tools and Architectures for Hardware/Software Co-Simulation of Reconfigurable SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 85-90
by Valery Sklyarov, Iouliia Skliarova, Bruno Pimentel, Manuel Almeida
A Modeling of a Dynamically Reconfigurable Processor Using SystemCFull-text access may be available. Sign in or learn about subscription options.pp. 91-96
by Junji Kitamichi, Koji Ueda, Kenichi Kuroda
Dynamic Aggregation of Virtual Addresses in TLB Using TCAM CellsFull-text access may be available. Sign in or learn about subscription options.pp. 243-248
by Rupak Samanta, Jason Surprise, Rabi Mahapatra
Energy-Efficient, High Performance Circuits for Arithmetic UnitsFull-text access may be available. Sign in or learn about subscription options.pp. 371-376
by Sundeepkumar Agarwal, V.K. Pavankumar, R. Yokesh
A Robust Level-Shifter Design for Adaptive Voltage ScalingFull-text access may be available. Sign in or learn about subscription options.pp. 383-388
by Ankur Gupta, Rajat Chauhan, Vinod Menezes, Vikas Narang, H.M. Roopashree
High-Level Modeling Approach for Analyzing the Effects of Traffic Models on Power and Throughput in Mesh-Based NoCsFull-text access may be available. Sign in or learn about subscription options.pp. 415-420
by S. Koohi, Mohammad Mirza-Aghatabar, Shaahin Hessabi, Masoud Pedram
Fault-Tolerant Computing Using a Hybrid Nano-CMOS ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 435-440
by Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivancic, Martin Roetteler, Niraj K. Jha
Energy Reduction in SRAM using Dynamic Voltage and Frequency ManagementFull-text access may be available. Sign in or learn about subscription options.pp. 503-508
by Mohammed Shareef I., Pradeep Nair, Bharadwaj Amrutur
Unified Vdd Vth Optimization Based DVFM Controller for a Logic BlockFull-text access may be available. Sign in or learn about subscription options.pp. 509-514
by S.A. Kannan, N.S. Sreeram, Bharadwaj S. Amrutur
Power Reduction of Functional Units Considering Temperature and Process VariationsFull-text access may be available. Sign in or learn about subscription options.pp. 533-539
by Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj, Sarma Vrudhula
A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/SubtractorFull-text access may be available. Sign in or learn about subscription options.pp. 547-552
by Sreehari Veeramachaneni, Kirthi Krishna M., G.V. Prateek, S. Subroto, S. Bharat, M.B. Srinivas
A Galois Field Based Logic Synthesis Approach with TestabilityFull-text access may be available. Sign in or learn about subscription options.pp. 629-634
by J. Mathew, H. Rahaman, A.K Singh, A.M. Jabir, D.K Pradhan
Single Chip Encryptor/Decryptor Core Implementation of AES AlgorithmFull-text access may be available. Sign in or learn about subscription options.pp. 693-698
by Monjur Alam, Santosh Ghosh, Dipanwita Roy Chowdhury, Indranil Sengupta
Power Attack Resistant Efficient FPGA Architecture for Karatsuba MultiplierFull-text access may be available. Sign in or learn about subscription options.pp. 706-711
by Chester Rebeiro, Debdeep Mukhopadhyay
Standards in EDA: An IntroductionFull-text access may be available. Sign in or learn about subscription options.pp. 727-727
by Nagi Naganathan
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