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2008 21st International Conference on VLSI Design

Jan. 4 2008 to Jan. 8 2008

Hyderabad

Table of Contents

21st International Conference on VLSI Design - CopyrightFreely available from IEEE.pp. iv
Introduction
Message from the General ChairsFreely available from IEEE.pp. xiv-xv
Introduction
Message from the Program ChairsFreely available from IEEE.pp. xvi-xvii
Introduction
Conference Steering CommitteeFreely available from IEEE.pp. xviii
Introduction
Conference CommitteeFreely available from IEEE.pp. xix-xxi
Introduction
Program CommitteeFreely available from IEEE.pp. xxii
Introduction
ReviewersFreely available from IEEE.pp. xxiii-xxviii
Introduction
FellowshipsFreely available from IEEE.pp. xxix-xxxiv
Introduction
VLSI Design 2007 AwardsFreely available from IEEE.pp. xxxv
Introduction
VLSI Design Conference HistoryFreely available from IEEE.pp. xxxvi
Introduction
Embedded Systems Design Conference HistoryFreely available from IEEE.pp. xxxvii
Introduction
Plenary Invited Keynote SpeakersFreely available from IEEE.pp. xxxviii-xxxix
Tutorials
Gateway to Chips: High Speed I/O Signalling and InterfaceFull-text access may be available. Sign in or learn about subscription options.pp. 3-4
by Nidhir Kumar, Senthil N. Velu, Rajan Verma
Tutorials
DFM / DFT / SiliconDebug / DiagnosisFull-text access may be available. Sign in or learn about subscription options.pp. 5-6
by Srikanth Venkataraman, Nagesh Tamarapalli
Tutorials
Oversampling Analog-to-Digital Converter DesignFull-text access may be available. Sign in or learn about subscription options.pp. 7
by Shanthi Pavan, Nagendra Krishnapura
Tutorials
Programming and Performance Modelling of Automotive ECU NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 8-9
by Samarjit Chakraborty, S. Ramesh
Tutorials
Architecture Exploration for Low Power DesignFull-text access may be available. Sign in or learn about subscription options.pp. 10-11
by Vinod Kathail, Tom Miller
Tutorials
Memory Design and Advanced Semiconductor TechnologyFull-text access may be available. Sign in or learn about subscription options.pp. 12
Tutorials
Scan Delay Testing of Nanometer SoCsFull-text access may be available. Sign in or learn about subscription options.pp. 13
by Adit D. Singh
Tutorials
Cross-Layer Approaches to Designing Reliable Systems Using Unreliable ChipsFull-text access may be available. Sign in or learn about subscription options.pp. 14-15
by Fadi Kurdahi, Nikil Dutt, Ahmed Eltawil, Sani Nassif
Tutorials
OpenSPARC - A Scalable Chip Multi-Threading DesignFull-text access may be available. Sign in or learn about subscription options.pp. 16
by Dwayne Lee
Tutorials
Implementing the Best Processor CoresFull-text access may be available. Sign in or learn about subscription options.pp. 17-18
by Vamsi Boppana, Rahoul Varma, S. Balajee
SESSION A1: Fault Tolerance
A Power Efficient Approach to Fault-Tolerant Register File DesignFull-text access may be available. Sign in or learn about subscription options.pp. 21-26
by Mojtaba Amiri-Kamalabad, Seyed Ghassem Miremadi, Mahdi Fazeli
SESSION A1: Fault Tolerance
Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOSFull-text access may be available. Sign in or learn about subscription options.pp. 27-32
by Maryam Ashouei, Adit D. Singh, Abhijit Chatterjee
SESSION A1: Fault Tolerance
Single Error Correcting Finite Field Multipliers Over GF(2m)Full-text access may be available. Sign in or learn about subscription options.pp. 33-38
by Jimson Mathew, A. Costas, A.M. Jabir, H. Rahaman, D.K. Pradhan
SESSION A1: Fault Tolerance
A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 39-44
by Aditya Jagirdar, Roystein Oliveira, Tapan Jyoti Chakraborty
SESSION A1: Fault Tolerance
Energy-Efficient Soft-Error Protection Using Operand Encoding and Operation BypassFull-text access may be available. Sign in or learn about subscription options.pp. 45-51
by Kaushal R. Gandhi, Nihar R. Mahapatr
SESSION B1: Wireless/Communication
Retimed Decomposed Serial Berlekamp-Massey (BM) Architecture for High-Speed Reed-Solomon DecodingFull-text access may be available. Sign in or learn about subscription options.pp. 53-58
by Shahid Rizwan
SESSION B1: Wireless/Communication
Exploring the Processor and ISA Design for Wireless Sensor Network ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 59-64
by Shashidhar Mysore, Banit Agrawal, Frederic T. Chong, Timothy Sherwood
SESSION B1: Wireless/Communication
Concurrent Multi-Dimensional Adaptation for Low-Power Operation in Wireless DevicesFull-text access may be available. Sign in or learn about subscription options.pp. 65-70
by Rajarajan Senguttuvan, Shreyas Sen, Abhijit Chatterjee
SESSION B1: Wireless/Communication
Adaptive Signal Scaling Driven Critical Path Modulation for Low Power Baseband OFDM ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 71-76
by Muhammad Mudassar Nisar, Rajarajan Senguttuvan, Abhijit Chatterjee
SESSION B1: Wireless/Communication
Fault Tolerant Dynamic Antenna Array in Smart Antenna System Using Evolved Virtual Reconfigurable CircuitFull-text access may be available. Sign in or learn about subscription options.pp. 77-83
by D. Dhanasekaran, K. Boopathy Bagan
SESSION C1: Embedded Systems
Multimedia Tools and Architectures for Hardware/Software Co-Simulation of Reconfigurable SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 85-90
by Valery Sklyarov, Iouliia Skliarova, Bruno Pimentel, Manuel Almeid
SESSION C1: Embedded Systems
A Modeling of a Dynamically Reconfigurable Processor Using SystemCFull-text access may be available. Sign in or learn about subscription options.pp. 91-96
by Junji Kitamichi, Koji Ueda, Kenichi Kurod
SESSION C1: Embedded Systems
A Scalable and Reconfigurable Coprocessor for Image CompositionFull-text access may be available. Sign in or learn about subscription options.pp. 97-102
by Jalaj Jain
SESSION C1: Embedded Systems
Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-ChipFull-text access may be available. Sign in or learn about subscription options.pp. 103-110
by Alexandru Andrei, Petru Eles, Zebo Peng, Jakob Rosen
SESSION C1: Embedded Systems
An Approach to Software Performance Evaluation on Customized Embedded ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 111-117
by Soumyajit Dey, Monu Kedia, Anupam Basu
SESSION D1: Technology
Compact Modeling of Suspended Gate FETFull-text access may be available. Sign in or learn about subscription options.pp. 119-124
by Yogesh Singh Chauhan, D. Tsamados, N. Abel?, C. Eggimann, M. Declercq, A.M. Ionescu
SESSION D1: Technology
Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate TechnologiesFull-text access may be available. Sign in or learn about subscription options.pp. 125-130
by Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy
SESSION D1: Technology
Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit DesignFull-text access may be available. Sign in or learn about subscription options.pp. 131-136
by Amith Singhee, Jiajing Wang, Benton H. Calhoun, Rob A. Rutenbar
SESSION D1: Technology
NBTI Degradation: A Problem or a Scare?Full-text access may be available. Sign in or learn about subscription options.pp. 137-142
by Kewal K. Saluja, Shriram Vijayakumar, Warin Sootkaneung, Xaingning Yang
SESSION D1: Technology
On-Chip Process Variation Detection Using Slew-Rate Monitoring CircuitFull-text access may be available. Sign in or learn about subscription options.pp. 143-149
by Amlan Ghosh, Rahul M. Rao, Jae-joon Kim, Ching-Te Chuang, Richard B. Brown
SESSION A2: Testing/DFT
On Common-Mode Skewed-Load and Broadside TestsFull-text access may be available. Sign in or learn about subscription options.pp. 151-156
by Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
SESSION A2: Testing/DFT
Testing Flash Memories for Tunnel Oxide DefectsFull-text access may be available. Sign in or learn about subscription options.pp. 157-162
by Mohammad Gh. Mohammad, Kewal K. Saluja
SESSION A2: Testing/DFT
On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test SetFull-text access may be available. Sign in or learn about subscription options.pp. 163-168
by Hafizur Rahaman, Dipak K. Kole, Debesh K. Das, Bhargab B. Bhattacharya
SESSION A2: Testing/DFT
Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault ModelsFull-text access may be available. Sign in or learn about subscription options.pp. 169-174
by Aman Kokrady, C.P. Ravikumar, Nitin Chandrachoodan
SESSION A2: Testing/DFT
Design-for-Testability for Improved Path Delay Fault Coverage of Critical PathsFull-text access may be available. Sign in or learn about subscription options.pp. 175-180
by Irith Pomeranz, Sudhakar M. Reddy
SESSION A2: Testing/DFT
Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching ActivityFull-text access may be available. Sign in or learn about subscription options.pp. 181-186
by Irith Pomeranz, Sudhakar M. Reddy
SESSION A2: Testing/DFT
A Partitioning Based Physical Scan Chain Allocation Algorithm that Minimizes Voltage Domain CrossingsFull-text access may be available. Sign in or learn about subscription options.pp. 187-193
by Nilabha Dev, Sandeep Bhatia, Subhasish Mukherjee, Sue Genova, Vinayak Kadam
SESSION B2: Interconnects
Wiring-Area Efficient Simultaneous Bidirectional Point-to-Point Link for Inter-Block On-Chip SignalingFull-text access may be available. Sign in or learn about subscription options.pp. 195-200
by Charbel J. Akl, Magdy A. Bayoumi
SESSION B2: Interconnects
Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable ProcessorFull-text access may be available. Sign in or learn about subscription options.pp. 201-207
by Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Diederik Verkest
SESSION B2: Interconnects
Integrated TIA-Equalizer for High Speed Optical LinkFull-text access may be available. Sign in or learn about subscription options.pp. 208-213
by Saurav Bandyopadhyay, Pradip Mandal, Stephen E. Ralph, Kenneth Pedrotti
SESSION B2: Interconnects
Single Edge Clock (SEC) Distribution for Improved Latency, Skew, and Jitter PerformanceFull-text access may be available. Sign in or learn about subscription options.pp. 214-219
by Jeff Mueller, Resve Saleh
SESSION B2: Interconnects
Threshold Voltage Control through Multiple Supply Voltages for Power-Efficient FinFET InterconnectsFull-text access may be available. Sign in or learn about subscription options.pp. 220-227
by Anish Muttreja, Prateek Mishra, Niraj K. Jha
SESSION B2: Interconnects
Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process VariationFull-text access may be available. Sign in or learn about subscription options.pp. 228-234
by Sampo Tuuna, Jouni Isoaho, Hannu Tenhunen
SESSION B2: Interconnects
Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect DesignFull-text access may be available. Sign in or learn about subscription options.pp. 235-241
by T. Venkata Kalyan, Madhu Mutyam, P. Vijaya Sankara Rao
SESSION C2: Architecture
Dynamic Aggregation of Virtual Addresses in TLB Using TCAM CellsFull-text access may be available. Sign in or learn about subscription options.pp. 243-248
by Rupak Samanta, Jason Surprise, Rabi Mahapatr
SESSION C2: Architecture
Continuous Frequency Adjustment Technique Based on Dynamic Workload PredictionFull-text access may be available. Sign in or learn about subscription options.pp. 249-254
by Hwisung Jung, Massoud Pedram
SESSION C2: Architecture
Recursive versus Iterative Algorithms for Solving Combinatorial Search Problems in HardwareFull-text access may be available. Sign in or learn about subscription options.pp. 255-260
by Iouliia Skliarova, Valery Sklyarov
SESSION C2: Architecture
Exhaustive Enumeration of Legal Custom Instructions for Extensible ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 261-266
by Nagaraju Pothineni, Anshul Kumar, Kolin Paul
SESSION C2: Architecture
An Optimal Multi-Functional Unit Dynamic Instruction Selection Logic at Submicron TechnologiesFull-text access may be available. Sign in or learn about subscription options.pp. 267-272
by Terrell Bennett, Rama Sangireddy
SESSION C2: Architecture
A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution CoresFull-text access may be available. Sign in or learn about subscription options.pp. 273-278
by Rajaraman Ramanarayanan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy, Shay Gueron
SESSION C2: Architecture
Dynamic Error Detection for Dependable Cache Coherency in Multicore ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 279-285
by Hui Wang, Sandeep Baldawa, Rama Sangireddy
SESSION D2: Analog
Mismatch Aware Analog Performance Macromodeling Using Spline Center and Range Regression on Adaptive SamplesFull-text access may be available. Sign in or learn about subscription options.pp. 287-293
by Shubhankar Basu, Balaji Kommineni, Ranga Vemuri
SESSION D2: Analog
An Input Stage for the Implementation of Low-Voltage Rail to Rail Offset Compensated CMOS ComparatorsFull-text access may be available. Sign in or learn about subscription options.pp. 294-299
by Jaime Ramirez-Angulo, Lalitha Mohana Kalyani-Garimella, Annajirao Garimella, Sri Raga Sudha Garimella, Antonio Lopez-Martin, Ramon Gonzalez Carvajal
SESSION D2: Analog
Highly Linear Wide Dynamic Swing CMOS Transconductance Multiplier Using Source-Degeneration V-I ConvertersFull-text access may be available. Sign in or learn about subscription options.pp. 300-304
by Sri Raga Sudha Garimell
SESSION D2: Analog
Chaos-Modulated Ramp IC for EMI Reduction in PWM Buck Converters- Design and Analysis of Critical IssuesFull-text access may be available. Sign in or learn about subscription options.pp. 305-310
by Rupam Mukherjee, Amit Patra, Soumitro Banerjee
SESSION D2: Analog
A Fast Settling 100dB OPAMP in 180nm CMOS Process with Compensation Based OptimisationFull-text access may be available. Sign in or learn about subscription options.pp. 311-316
by Amal Kumar Kundu, Subho Chatterjee, Tarun Kanti Bhattacharyya
SESSION D2: Analog
VLSI Implementation of a Digitally Tunable Gm-C Filter with Double CMOS PairFull-text access may be available. Sign in or learn about subscription options.pp. 317-322
by S. Ramasamy, B. Venkataramani, K. Anbugeetha
SESSION D2: Analog
A 9 bit 400 MHz CMOS Double-Sampled Sample-and-Hold AmplifierFull-text access may be available. Sign in or learn about subscription options.pp. 323-329
by Sounak Roy, Swapna Banerjee
SESSION A3: Physical Design/CAD
A New Approach for Estimation of On-Resistance and Current Distribution in Power Array LayoutsFull-text access may be available. Sign in or learn about subscription options.pp. 331-336
by Jyotirmoy Ghosh, Siddhartha Mukhopadhyay, Amit Patra, Barry Culpepper, Tawen Mei
SESSION A3: Physical Design/CAD
An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI FloorplanningFull-text access may be available. Sign in or learn about subscription options.pp. 337-342
by Pradeep Fernando, Srinivas Katkoori
SESSION A3: Physical Design/CAD
Fast Congestion Aware Routing for Pin AssignmentFull-text access may be available. Sign in or learn about subscription options.pp. 343-347
by Shashank Prasad
SESSION A3: Physical Design/CAD
A Novel Approach to Compute Spatial Reuse in the Design of Custom InstructionsFull-text access may be available. Sign in or learn about subscription options.pp. 348-353
by Nagaraju Pothineni, Anshul Kumar, Kolin Paul
SESSION A3: Physical Design/CAD
Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software CosimulationFull-text access may be available. Sign in or learn about subscription options.pp. 354-361
by Banit Agrawal, Timothy Sherwood, Chulho Shin, Simon Yoon
SESSION B3: Low Power - I
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 363-370
by Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil Dutt
SESSION B3: Low Power - I
Energy-Efficient, High Performance Circuits for Arithmetic UnitsFull-text access may be available. Sign in or learn about subscription options.pp. 371-376
by Sundeepkumar Agarwal, Pavankumar V K, Yokesh R
SESSION B3: Low Power - I
Delay and Energy Efficient Design of On-Chip Encoded Bus with RepeatersFull-text access may be available. Sign in or learn about subscription options.pp. 377-382
by Qingli Zhang, Jinxiang Wang, Yizheng Ye
SESSION B3: Low Power - I
A Robust Level-Shifter Design for Adaptive Voltage ScalingFull-text access may be available. Sign in or learn about subscription options.pp. 383-388
by Ankur Gupta, Rajat Chauhan, Vinod Menezes, Vikas Narang, Roopashree H.M.
SESSION B3: Low Power - I
Low Power Hardware Architecture for VBSME Using Pixel TruncationFull-text access may be available. Sign in or learn about subscription options.pp. 389-395
by Asral Bahari, Tughrul Arslan, Ahmet T. Erdogan
SESSION C3: NoC/SoC
MoCSYS: A Multi-Clock Hybrid Two-Layer Router Architecture and Integrated Topology Synthesis Framework for System-Level Design of FPGA Based On-Chip NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 397-402
by Arun Janarthanan, Karen A. Tomko
SESSION C3: NoC/SoC
MPSoC Communication Architecture Exploration Using an Abstraction Refinement MethodFull-text access may be available. Sign in or learn about subscription options.pp. 403-408
by Hao Shen, Frederic Petrot
SESSION C3: NoC/SoC
An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage ConsiderationsFull-text access may be available. Sign in or learn about subscription options.pp. 409-414
by Mahshid Sedghi, Elnaz Koopahi, Armin Alaghi, Mahmood Fathy, Zainalabedin Navabi
SESSION C3: NoC/SoC
High-Level Modeling Approach for Analyzing the Effects of Traffic Models on Power and Throughput in Mesh-Based NoCsFull-text access may be available. Sign in or learn about subscription options.pp. 415-420
by Somayyeh Koohi, Mohammad Mirza-Aghatabar, Shaahin Hessabi, Masoud Pedram
SESSION C3: NoC/SoC
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 421-427
by Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nikil D. Dutt, Fadi J. Kurdahi
SESSION D3: Nano
Single Event Upset: An Embedded TutorialFull-text access may be available. Sign in or learn about subscription options.pp. 429-434
by Fan Wang, Vishwani D. Agrawal
SESSION D3: Nano
Fault-Tolerant Computing Using a Hybrid Nano-CMOS ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 435-440
by Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivancic, Martin Roetteler, Niraj K. Jha
SESSION D3: Nano
Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 441-446
by Rajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia
SESSION D3: Nano
A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire TransistorFull-text access may be available. Sign in or learn about subscription options.pp. 447-452
by Biswajit Ray, Santanu Mahapatra
SESSION D3: Nano
Design of Reversible Finite Field Arithmetic Circuits with Error DetectionFull-text access may be available. Sign in or learn about subscription options.pp. 453-459
by Jimson Mathew, Hafizur Rahaman, Babita R. Jose, Dhiraj K. Pradhan
SESSION A4: Verification
Exploiting Circuit Reconvergence through Static Learning in CNF SAT SolversFull-text access may be available. Sign in or learn about subscription options.pp. 461-468
by Yinlei Yu, Cameron Brien, Sharad Malik
SESSION A4: Verification
Efficient Linear Macromodeling via Discrete-Time Time-Domain Vector FittingFull-text access may be available. Sign in or learn about subscription options.pp. 469-474
by Chi-Un Lei, Ngai Wong
SESSION A4: Verification
Formal Verification of a Public-Domain DDR2 Controller DesignFull-text access may be available. Sign in or learn about subscription options.pp. 475-480
by Abhishek Datta, Vigyan Singhal
SESSION A4: Verification
Enhanced TED: A New Data Structure for RTL VerificationFull-text access may be available. Sign in or learn about subscription options.pp. 481-486
by Pejman Lotfi-Kamran, Mehran Massoumi, Mohammad Mirzaei, Zainalabedin Navabi
SESSION A4: Verification
Simulation Acceleration with HW Re-Compilation AvoidanceFull-text access may be available. Sign in or learn about subscription options.pp. 487-491
by Kyuho Shim, Kesava Talupuru, Maciej Ciesielski, Seiyang Yang
SESSION A4: Verification
A Module Checking Based Converter Synthesis Approach for SoCsFull-text access may be available. Sign in or learn about subscription options.pp. 492-501
by Roopak Sinha, Partha S. Roop, Samik Basu
SESSION B4: Low Power - II
Energy Reduction in SRAM using Dynamic Voltage and Frequency ManagementFull-text access may be available. Sign in or learn about subscription options.pp. 503-508
by Mohammed Shareef I, Pradeep Nair, Bharadwaj Amrutur
SESSION B4: Low Power - II
Unified Vdd - Vth Optimization Based DVFM Controller for a Logic BlockFull-text access may be available. Sign in or learn about subscription options.pp. 509-514
by Kannan S.A., Sreeram N.S., Bharadwaj S. Amrutur
SESSION B4: Low Power - II
Temperature and Process Variations Aware Power Gating of Functional UnitsFull-text access may be available. Sign in or learn about subscription options.pp. 515-520
by Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma Vrudhula
SESSION B4: Low Power - II
A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 521-526
by Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri
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