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2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID)

Jan. 4 2020 to Jan. 8 2020

Bangalore, India

ISBN: 978-1-7281-5701-6

Table of Contents

VLSID 2020 CommentaryFreely available from IEEE.pp. i-i
VLSID 2020 CommentaryFreely available from IEEE.pp. i-i
VLSID 2020 Breaker PageFreely available from IEEE.pp. i-i
VLSID 2020 TOCFreely available from IEEE.pp. i-v
Message from the General Co-ChairsFreely available from IEEE.pp. i-i
by Sumit Goswami, Veeresh Shetty
Message from the Technical Program Co-ChairsFreely available from IEEE.pp. i-i
by David Atienza, Subhasish Mitra, Manan Suri
Message from the Tutorial Co-ChairsFreely available from IEEE.pp. i-i
by Amir Aminifar, Shabbir Batterywala
Message from the Steering Committee ChairFreely available from IEEE.pp. i-i
by Vishwani D. Agrawal
About the Cover from the Publication Co-ChairsFreely available from IEEE.pp. i-i
VLSID 2020 CommitteesFreely available from IEEE.pp. i-i
VLSI Design and Embedded Systems 2020 Conference CommitteeFreely available from IEEE.pp. i-iii
VLSID 2020 Technical Program CommitteeFreely available from IEEE.pp. i-iv
VLSI Design Conference HistoryFreely available from IEEE.pp. i-ii
VLSID 2020 CommitteesFreely available from IEEE.pp. i-i
Keynote: Technology directions for a bright semiconductor futureFull-text access may be available. Sign in or learn about subscription options.pp. 1-8
by Suk Lee
Tutorial: Open-Source EDA and Machine Learning for IC Design: A Live UpdateFull-text access may be available. Sign in or learn about subscription options.pp. 1-14
by Abdelrahman Hosny, Andrew B. Kahng
Invited Talk: Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, and SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 1-18
by Priyadarshini Panda, Kaushik Roy
A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder for 5G New-RadioFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Anuj Verma, Rahul Shrestha
Power Efficient Sense Amplifier For Emerging Non Volatile MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 7-12
by Vivek Tyagi, Vikas Rana, Laura Capecchi, Marcella Carissimi, Marco Pasotti
Fault Tolerance through Invariant Checking for the Lanczos EigensolverFull-text access may be available. Sign in or learn about subscription options.pp. 13-18
by Felix Loh, Kewal K. Saluja, Parameswaran Ramanathan
Non-parametric Statistical Density Function Synthesizer and Monte Carlo Sampler in CMOSFull-text access may be available. Sign in or learn about subscription options.pp. 19-24
by Ahish Shylendra, Sina Haji Alizad, Priyesh Shukla, Amit Ranjan Trivedi
A Novel Low Power Ternary Multiplier Design using CNFETsFull-text access may be available. Sign in or learn about subscription options.pp. 25-30
by Harita Sirugudi, Sharvani Gadgil, Chetan Vudadha
3.75ppm/°C, -91dB PSRR, 27nW, 0.9V PVT Invariant Voltage Reference for Implantable Biomedical ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 31-36
by Mounika Kelam, Balaji Yadav Battu, Zia Abbas
Design of Sense Amplifier for Wide Voltage Range Operation of Split Supply Memories in 22nm HKMG CMOS TechnologyFull-text access may be available. Sign in or learn about subscription options.pp. 37-42
by Vinay Patil, Anuj Grover, Anuj Parashar
User-centric Resource Management for Embedded Multi-core ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 43-48
by Elham Shamsa, Anil Kanduri, Nima TaheriNejad, Alma Pröbstl, Samarjit Chakraborty, Amir M. Rahmani, Pasi Liljeberg
Runtime Monitoring of Inter- and Intra-Thread Requirements on Embedded MPSoCsFull-text access may be available. Sign in or learn about subscription options.pp. 49-54
by Marcel Mettler, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Efficient Quantum Circuits for Square-Root and Inverse Square-RootFull-text access may be available. Sign in or learn about subscription options.pp. 55-60
by Srijit Dutta, Yaswanth Tavva, Debjyoti Bhattacharjee, Anupam Chattopadhyay
Alternative Reduced Hardware MASHI-I-I Digital Delta Sigma ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 61-66
by Prasad Kulkarni
Enhancing the Phase-Noise-Figure-of-Merit of a Resonator using Frequency TransformationsFull-text access may be available. Sign in or learn about subscription options.pp. 67-71
by Sreeni Poolakkal, Nagarjuna Nallam
The Design of Ultra Low Power SAR ADC for Implantable Cardioverter Defibrillator (ICD)Full-text access may be available. Sign in or learn about subscription options.pp. 72-77
by Satyajit Mohapatra, Nihar Ranjan Mohapatra
A Shared-Memory Parallel Implementation of the RePlAce Global Cell PlacerFull-text access may be available. Sign in or learn about subscription options.pp. 78-83
by Frédéric Gessler, Philip Brisk, Mirjana Stojilovič
A Sub-Range Error Characterization based Selection Methodology for Approximate Arithmetic UnitsFull-text access may be available. Sign in or learn about subscription options.pp. 84-89
by Hassaan Saadat, Tuo Li, Haris Javaid, Sri Parameswaran
Area and Energy Efficient Approximate Square Rooters for Error Resilient ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 90-95
by Neelam Arya, Teena Soni, Manisha Pattanaik, G.K. Sharma
A 36dB Gain Range, 0.5dB Gain Step Variable Gain Amplifier with 10 to 25MHz Bandwidth Third-Order Filter for Portable Ultrasound SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 96-100
by Purnendu Bhattaru, Nagendra Krishnapura
A Low Overhead Methodology for Validating Memory Consistency Models in Chip MultiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 101-106
by Binod Kumar, Swapniel Thakur, Kanad Basu, Masahiro Fujita, Virendra Singh
Analyzing Hardware Security Properties of Processors through Model CheckingFull-text access may be available. Sign in or learn about subscription options.pp. 107-112
by Binod Kumar, Akshay Kumar Jaiswal, V S Vineesh, Rushikesh Shinde
VLSI based Adaptive Power Management Architecture for ECG Monitoring in WBANFull-text access may be available. Sign in or learn about subscription options.pp. 113-118
by Jitumani Sarma, Rakesh Biswas
CoveRT: A Coverage Reporting Tool for Analog Mixed-Signal DesignsFull-text access may be available. Sign in or learn about subscription options.pp. 119-124
by Sayandeep Sanyal, Aritra Hazra, Pallab Dasgupta, Scott Morrison, Sudhakar Surendran, Lakshmanan Balasubramanian
Thermal Load-aware Adaptive Scheduling for Heterogeneous PlatformsFull-text access may be available. Sign in or learn about subscription options.pp. 125-130
by Srijeeta Maity, Anirban Ghose, Soumyajit Dey, Swarnendu Biswas
FPGA-Based Acceleration of LU decomposition for Analog and RF Circuit SimulationFull-text access may be available. Sign in or learn about subscription options.pp. 131-136
by Yogesh Mahajan, Shashank Obla, Mini K. Namboothiripad, Mandar J. Datar, Niraj N. Sharma, Sachin B. Patkar
Cacheline Utilization-Aware Link Traffic Compression for Modular GPUsFull-text access may be available. Sign in or learn about subscription options.pp. 137-142
by Kishore Punniyamurthy, Shomit Das, Andreas Gerstlauer
A Multi-Agent Co-operative Model to Facilitate Criticality based Reliability for Mixed Critical Task Execution on FPGA based Cloud EnvironmentFull-text access may be available. Sign in or learn about subscription options.pp. 143-148
by Krishnendu Guha, Debasri Saha, Amlan Chakrabarti
Dissecting Convolutional Neural Networks for Efficient Implementation on Constrained PlatformsFull-text access may be available. Sign in or learn about subscription options.pp. 149-154
by Vishalini R. Laguduva, Shakil Mahmud, Sathyanarayanan N. Aakur, Robert Karam, Srinivas Katkoori
E2GC: Energy-efficient Group Convolution in Deep Neural NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 155-160
by Nandan Kumar Jha, Rajat Saini, Subhrajit Nag, Sparsh Mittal
A Low Noise, Low Power, Wide Range Programmable Output Reference Buffer for Sensor ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 161-164
by Prudhvi Raj Thota, Kiran Wadagavi, Namani Rakesh, Sumit Bhat, Abirmoya Santra
A Novel Methodology of PWM/PFM Mode Transition for Inverting Buck-Boost and Boost Converter for AMOLED Display ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 165-170
by Venkatesh Kadlimatti, Prudhvi Thota, Sumit Bhat
StateLock: State Transition Based Logic Locking for Sequential CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 171-176
by Yasaswy Kasarabada, Ranga Vemuri
A Mathematical Approach Towards Quantization of Floating Point Weights in Low Power Neural NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 177-182
by Joydeep Kumar Devnath, Neelam Surana, Joycee Mekie
FPGA based convolution and memory architecture for Convolutional Neural NetworkFull-text access may be available. Sign in or learn about subscription options.pp. 183-188
by K A Shahan, J Sheeba Rani
On the Effect of Aging on Digital SensorsFull-text access may be available. Sign in or learn about subscription options.pp. 189-194
by Md Toufiq Hasan Anik, Sylvain Guilley, Jean-Luc Danger, Naghmeh Karimi
Intensifying Challenge Obfuscation by Cascading FPGA RO-PUFs for Random Number GenerationFull-text access may be available. Sign in or learn about subscription options.pp. 195-200
by Arjun Singh Chauhan, Vineet Sahula, A. S. Mandal, Abhigyan Dutta
Leveraging Dynamic Partial Reconfiguration with Scalable ILP Based Task SchedulingFull-text access may be available. Sign in or learn about subscription options.pp. 201-206
by Ashutosh Dhar, Mang Yu, Wei Zuo, Xiaohao Wang, Nam Sung Kim, Deming Chen
A Novel Parametrized Fused Division and Square-Root POSIT Arithmetic ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 207-212
by Aneesh Raveendran, Sandra Jean, J. Mervin, D. Vivian, David Selvakumar
A Design Optimization for Pin-Constrained Paper-based Digital Microfluidic Biochips Integrating Fluid-Control Co-Design IssuesFull-text access may be available. Sign in or learn about subscription options.pp. 213-218
by Piyali Datta, Arpan Chakraborty, Rajat Kumar Pal
An Accurate, Power and Area Efficient 13.33x Charge Pump with Wide-Range Programmability for Biomedical SensorsFull-text access may be available. Sign in or learn about subscription options.pp. 219-224
by Amit Patil, Sumit Bhat, Abirmoya Santra
VLSID 2020 IndexFreely available from IEEE.pp. i-ii
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