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Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)

April 28 2002 to May 2 2002

Monterey, CA, USA

Table of Contents

ForewordFreely available from IEEE.pp. xvi
VTS 20th Anniversary PageFull-text access may be available. Sign in or learn about subscription options.pp. xvii
AcknowledgementsFreely available from IEEE.pp. xviii
Organizing CommitteeFreely available from IEEE.pp. xix
Steering CommitteeFreely available from IEEE.pp. xxii
Program CommitteeFreely available from IEEE.pp. xxiii
ReviewersFreely available from IEEE.pp. xxiv
Test Technology Technical CouncilFull-text access may be available. Sign in or learn about subscription options.pp. xxvii
Test Technology Educational Program: Overview of TutorialsFreely available from IEEE.pp. xxx
Welcome Message: Joan Figueras, General Chair
Keynote AddressFreely available from IEEE.pp. xxxv
by Michael Hackworth
Program Introduction: Andre Ivanov, Program Chair
Plenary Address: Business and Technical Challenges for Testing the Ghz AgeFull-text access may be available. Sign in or learn about subscription options.pp. xxxvii
by Jai K. Hakhu
Session 1: Microprocessor Test: Moderators: M. d'Abreau, Ample Communications
Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 0003
by Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich
Test hardware design challenges in RF testingFull-text access may be available. Sign in or learn about subscription options.pp. 172-172
by M. Slamani, H. Ding
Session 1: Microprocessor Test: Moderators: M. d'Abreau, Ample Communications
Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based DesignsFull-text access may be available. Sign in or learn about subscription options.pp. 0009
by Amit R. Pandey, Tanak H. Patel
Programmable embedded IF source for wireless testFull-text access may be available. Sign in or learn about subscription options.pp. 172-172
by W.R. Eisenstadt, Sanghoon Choi
Session 1: Microprocessor Test: Moderators: M. d'Abreau, Ample Communications
Scan Islands - A Scan Partitioning Architecture and its Implementation on the Alpha 21364 ProcessorFull-text access may be available. Sign in or learn about subscription options.pp. 0016
by Dilip K. Bhavsar, Richard A. Davies
Open problems in wireless test and why you should careFull-text access may be available. Sign in or learn about subscription options.pp. 172-172
by J. McLaughlin
Session 2: Applications of Very Low Voltage and Slow Speed Testing: Moderators: K. Eshraghian, Edith Cowan University
Very Low Voltage Testing of SOI Integrated CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 0025
by Eric MacDonald, Nur A. Touba
Session 2: Applications of Very Low Voltage and Slow Speed Testing: Moderators: K. Eshraghian, Edith Cowan University
Performance Comparison of VLV, ULV, and ECR TestsFull-text access may be available. Sign in or learn about subscription options.pp. 0031
by Wanli Jiang, Eric Peterson
Session 2: Applications of Very Low Voltage and Slow Speed Testing: Moderators: K. Eshraghian, Edith Cowan University
Experimental Results for Slow-Speed TestingFull-text access may be available. Sign in or learn about subscription options.pp. 0037
by Chao-Wen Tseng, James Li, Edward J. McCluskey
IP Session 1: Innovations in Test Automation
Innovations in Test AutomationFull-text access may be available. Sign in or learn about subscription options.pp. 0043
by J. Borel, Anand Raghunathan, Jim Sproch, Michael Howells, Janusz Rajski
Session 3: Advancements in Scan-Based Testing: Moderators: M. Lousberg, Philips
Scan-Path with Directly Duplicated and Inverted Duplicated RegistersFull-text access may be available. Sign in or learn about subscription options.pp. 0047
by M. Goessel, E. Sogomonyan, A. Singh
Session 3: Advancements in Scan-Based Testing: Moderators: M. Lousberg, Philips
An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 0053
by Aiman El-Maleh, Ali Al-Suwaiyan
Session 3: Advancements in Scan-Based Testing: Moderators: M. Lousberg, Philips
Logic BIST and Scan Test Techniques for Multiple Identical BlocksFull-text access may be available. Sign in or learn about subscription options.pp. 0060
by Karim Arabi
Session 4: Burn-in Reduction or Alternatives: Moderators: K. Mandl, Teradyne
Statistical Post-Processing at Wafersort - An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micron TechnologiesFull-text access may be available. Sign in or learn about subscription options.pp. 0069
by Robert Madge, Manu Rehani, Kevin Cota, W. Robert Daasch
Session 4: Burn-in Reduction or Alternatives: Moderators: K. Mandl, Teradyne
Yield-Reliability Modeling: Experimental Verification and Application to Burn-In ReductionFull-text access may be available. Sign in or learn about subscription options.pp. 0075
by Thomas S. Barnett, Adit D. Singh, Matt Grady, Kathleen Purdy
Session 4: Burn-in Reduction or Alternatives: Moderators: K. Mandl, Teradyne
Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in ReductionFull-text access may be available. Sign in or learn about subscription options.pp. 0081
by Sagar S. Sabade, Duncan M. Walker
IP Session 2: DFT Testers 1
A Successful DFT Tester: What Will It Look Like? Is Revolution in Test Approaches Required?Full-text access may be available. Sign in or learn about subscription options.pp. 0087
by Lee Song, Rudy Garcia, Andrew Levy, Don Wheater
Session 5: Test Set Compression Techniques: Moderators: K. Butler, Texas Instruments
How Effective are Compression Codes for Reducing Test Data Volume?Full-text access may be available. Sign in or learn about subscription options.pp. 0091
by Anshuman Chandra, Krishnendu Chakrabarty, Rafael A. Medina
Session 5: Test Set Compression Techniques: Moderators: K. Butler, Texas Instruments
Test Vector Compression Using EDA-ATE SynergiesFull-text access may be available. Sign in or learn about subscription options.pp. 0097
by Ajay Khoche, Erik Volkerink, Jochen Rivoir, Subhasish Mitra
Session 5: Test Set Compression Techniques: Moderators: K. Butler, Texas Instruments
On Test Data Volume Reduction for Multiple Scan Chain DesignsFull-text access may be available. Sign in or learn about subscription options.pp. 0103
by Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz
Session 6: Analog BIST: Moderators: J. da Franca, ChipIdea
Spectrum-Based BIST in Complex SOCsFull-text access may be available. Sign in or learn about subscription options.pp. 0111
by Ganapathy Kasturirangan, Michael S. Hsiao
Session 6: Analog BIST: Moderators: J. da Franca, ChipIdea
A Self Calibrated ADC BIST MethodologyFull-text access may be available. Sign in or learn about subscription options.pp. 0117
by Hung-kai Chen, Chih-hu Wang, Chau-chin Su
Session 6: Analog BIST: Moderators: J. da Franca, ChipIdea
Self-Testing Second-Order Delta-Sigma Modulators Using Digital StimulusFull-text access may be available. Sign in or learn about subscription options.pp. 0123
by Chee-Kian Ong, Kwang-Ting (Tim) Cheng
A successful DFT tester: what will it look like? Is DFT tester a logical next step in ATE evolution?Full-text access may be available. Sign in or learn about subscription options.pp. 129-129
by Lee Song, P. Patton, W. Radermacher
Session 7: Increased Efficiency Testing: Moderators: B. Pouya, Banderacom
Testing High-Speed SoCs Using Low-Speed ATEsFull-text access may be available. Sign in or learn about subscription options.pp. 0133
by Mehrdad Nourani, James Chin
Session 7: Increased Efficiency Testing: Moderators: B. Pouya, Banderacom
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCsFull-text access may be available. Sign in or learn about subscription options.pp. 0139
by Madhu K. Iyer, Kwang-Ting Cheng
Session 7: Increased Efficiency Testing: Moderators: B. Pouya, Banderacom
On Using Efficient Test Sequences for BISTFull-text access may be available. Sign in or learn about subscription options.pp. 0145
by R. David, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel
Session 8: Controlling and Reducing Test Power: Moderators: A. Crouch, Inovys
Controlling Peak Power During Scan TestingFull-text access may be available. Sign in or learn about subscription options.pp. 0153
by Ranganathan Sankaralingam, Nur A. Touba
Session 8: Controlling and Reducing Test Power: Moderators: A. Crouch, Inovys
Test Vector Modification for Power Reduction during Scan TestingFull-text access may be available. Sign in or learn about subscription options.pp. 0160
by Seiji Kajihara, Koji Ishida, Kohei Miyase
Session 8: Controlling and Reducing Test Power: Moderators: A. Crouch, Inovys
Test Power Reduction through Minimization of Scan Chain TransitionsFull-text access may be available. Sign in or learn about subscription options.pp. 0166
by Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu
IP Session 4
Wireless TestFull-text access may be available. Sign in or learn about subscription options.pp. 0173
by Robert Aitken, Mustapha Slamani, H. Ding, William R. Eisenstadt, Sanghoon Choi, John McLaughlin
Analog and mixed signal BIST: too much, too little, too late? [panel session]Freely available from IEEE.pp. 175-175
by W. DeWilkins, B. Baril, A. Osseiran, F. Muradali, S. Tabatabaei, K. Posse, Lee Song
Special Session 2: Panel
Test as a Key Enabler for Faster Yield Ramp-UpFull-text access may be available. Sign in or learn about subscription options.pp. 0177
by Julie Segal, Rene Segers, R. Aitke, S. Eichenberge, A. Gattike, M. Millegen, R. Seger, S. Venkataraman
Session 9: Diagnosis: Moderators: F. Maamari, LogicVision
Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 0181
by M. Enamul Amyeen, Irith Pomeranz, W. Kent Fuchs
Session 9: Diagnosis: Moderators: F. Maamari, LogicVision
Diagnosis of Sequence-Dependent ChipsFull-text access may be available. Sign in or learn about subscription options.pp. 0187
by James C.-M. Li, E. J. McCluskey
Session 9: Diagnosis: Moderators: F. Maamari, LogicVision
Speeding Up The Byzantine Fault Diagnosis Using Symbolic SimulationFull-text access may be available. Sign in or learn about subscription options.pp. 0193
by Shi-Yu Huang
Session 10: Analog Circuit Testing: Moderators: J. Abraham, University of Texas at Austin
Filters Designed for Testability Wrapped on the Mixed-Signal Test BusFull-text access may be available. Sign in or learn about subscription options.pp. 0201
by Jose Vicente Calvano, Vladimir Castro Alves, Antonio C. Mesquita, Marcelo Lubaszewski
Session 10: Analog Circuit Testing: Moderators: J. Abraham, University of Texas at Austin
Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency DivisionFull-text access may be available. Sign in or learn about subscription options.pp. 0207
by Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha
Session 10: Analog Circuit Testing: Moderators: J. Abraham, University of Texas at Austin
Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance AnalysisFull-text access may be available. Sign in or learn about subscription options.pp. 0213
by Sule Ozev, Alex Orailoglu
Session 11: High Level Test Techniques: Moderators: J. Aylor, Virginia Tech
Instruction-Based Self-Testing of Processor CoresFull-text access may be available. Sign in or learn about subscription options.pp. 0223
by N. Kranitis, A. Paschalis, D. Gizopoulos, Y. Zorian
An industrial environment for high-level fault-tolerant structures insertion and validationFull-text access may be available. Sign in or learn about subscription options.pp. 229-236
by L. Berrojo, F. Corno, L. Entrena, I. Gonzalez, C. Lopez, M. Sonza Reorda, G. Squillero
Session 11: High Level Test Techniques: Moderators: J. Aylor, Virginia Tech
Program Slicing for Hierarchical Test GenerationFull-text access may be available. Sign in or learn about subscription options.pp. 0237
by Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra
Session 12: SoC Test Infrastructure: Moderators: M. Mowji, LogicVision
Design for Testability and Testing of IEEE 1149.1 Tap ControllerFull-text access may be available. Sign in or learn about subscription options.pp. 0247
by Subhasish Mitra, Edward J. McCluskey, Samy Makar
Session 12: SoC Test Infrastructure: Moderators: M. Mowji, LogicVision
On Using Rectangle Packing for SOC Wrapper/TAM Co-OptimizationFull-text access may be available. Sign in or learn about subscription options.pp. 0253
by Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
Session 12: SoC Test Infrastructure: Moderators: M. Mowji, LogicVision
Cluster-Based Test Architecture Design for System-on-ChipFull-text access may be available. Sign in or learn about subscription options.pp. 0259
by Sandeep Kumar Goel, Erik Jan Marinissen
IP Session 5: Multi-GigaHertz Testing Challenges and Solutions
Multi-GigaHertz Testing Challenges and SolutionsFull-text access may be available. Sign in or learn about subscription options.pp. 0265
by Karim Arabi, Klaus-Dieter Hilliges, David Keezer, Sassan Tabatabaei
Session 13: Test Tools and Algorithms: Moderators: T. Williams, Synopsys
Exploiting Dominance and Equivalence using Fault TuplesFull-text access may be available. Sign in or learn about subscription options.pp. 0269
by Kumar N. Dwarakanat, R. D. (Shawn) Blanton
Session 13: Test Tools and Algorithms: Moderators: T. Williams, Synopsys
Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs?Full-text access may be available. Sign in or learn about subscription options.pp. 0275
by Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham
Session 13: Test Tools and Algorithms: Moderators: T. Williams, Synopsys
RAMSES-FT: A Fault Simulator for Flash Memory Testing and DiagnosticsFull-text access may be available. Sign in or learn about subscription options.pp. 0281
by Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu
Session 14: Supply Current Testing: Moderators: T. Storey, PDF
Eigen-Signatures for Regularity-based IDDQ TestingFull-text access may be available. Sign in or learn about subscription options.pp. 0289
by Yukio Okuda
Session 14: Supply Current Testing: Moderators: T. Storey, PDF
Speeding-Up IDDQ MeasurementsFull-text access may be available. Sign in or learn about subscription options.pp. 0295
by C. Thibeault
Session 14: Supply Current Testing: Moderators: T. Storey, PDF
Dynamic Supply Current Testing of Analog Circuits Using Wavelet TransformFull-text access may be available. Sign in or learn about subscription options.pp. 0302
by Swarup Bhunia, Kaushik Roy
Special Session 3: Panel
Debating the Future of Burn-InFull-text access may be available. Sign in or learn about subscription options.pp. 0311
by Edward J. McCluske, Subhasish Mitra, Bob Madge, Peter Maxwell, Phil Nigh, Mike Rodgers
Special Session 4: Hot Topic
Beyond CMOSFull-text access may be available. Sign in or learn about subscription options.pp. 315
by M. Forshaw
Special Session 5: Embedded Tutorial
Challenges of Mixed-Signal Board Design and TestFull-text access may be available. Sign in or learn about subscription options.pp. 0317
by G. Roberts
Session 15: Test Pattern Generation: Moderators: J. Hayes, University of Michigan
A Method of Test Generation for Path Delay Faults in Balanced Sequential CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 0321
by Satoshi Ohtake, Hideo Fujiwara, Shunjiro Miwa
Session 15: Test Pattern Generation: Moderators: J. Hayes, University of Michigan
A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 0328
by Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka
Session 15: Test Pattern Generation: Moderators: J. Hayes, University of Michigan
Test Pattern Generation for Signal Integrity Faults on Long InterconnectsFull-text access may be available. Sign in or learn about subscription options.pp. 0336
by Amir Attarha, Mehrdad Nourani
Session 16: Tester Hardware Modeling and Improvements: Moderators: M. Topsakal, Cypress
Improved Test Monitor Circuit in Power Pin DfTFull-text access may be available. Sign in or learn about subscription options.pp. 0345
by Rodger Schuttert, Frans de Jong, Ben Kup
Session 16: Tester Hardware Modeling and Improvements: Moderators: M. Topsakal, Cypress
Measuring stray capacitance on tester hardwareFull-text access may be available. Sign in or learn about subscription options.pp. 351-356
by A. Halder, P. Variyam, A. Chatterjee, J. Ridley
Session 16: Tester Hardware Modeling and Improvements: Moderators: M. Topsakal, Cypress
Power Supply Transient Signal Analysis Under Real Process and Test Hardware ModelsFull-text access may be available. Sign in or learn about subscription options.pp. 0357
by Abhishek Singh, Jim Plusquellic, Anne Gattiker
Session 17: Fault Modeling & Extraction: Moderators: G. Robinson, 3MTS
Layout Analysis to Extract Open Nets Caused by Systematic Failure MechanismsFull-text access may be available. Sign in or learn about subscription options.pp. 0367
by Sreejit Chakravarty, Kambiz Komeyli, Eric W. Savage, Michael J. Carruthers, Bret T. Stastny, Sujit T. Zachariah
Session 17: Fault Modeling & Extraction: Moderators: G. Robinson, 3MTS
Fault Models for Speed Failures Caused by Bridges and OpensFull-text access may be available. Sign in or learn about subscription options.pp. 0373
by Sreejit Chakravarty, Ankur Jain
Session 17: Fault Modeling & Extraction: Moderators: G. Robinson, 3MTS
Timed Test Generation Crosstalk Switch Failures in Domino CMOS CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 0379
by Rahul Kundu, R. D. (Shawn) Blanton
Session 18: Memory Testing: Moderators: N. Saxena, Chip Engines
Testing and Diagnosing Embedded Content Addressable MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 0389
by Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu
Session 18: Memory Testing: Moderators: N. Saxena, Chip Engines
Testing Static and Dynamic Faults in Random Access MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 0395
by Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor
Session 18: Memory Testing: Moderators: N. Saxena, Chip Engines
Approximating Infinite Dynamic Behavior for DRAM Cell DefectsFull-text access may be available. Sign in or learn about subscription options.pp. 0401
by Zaid Al-Ars, Ad J. van de Goor
IP Session 8
Validation and Test of Network Processors and ASICsFull-text access may be available. Sign in or learn about subscription options.pp. 0407
by C.-H. Chia, Sujit Dey, Faraydon Karim, Haluk Konuk, Keesup Kim
Session 19: Test-Cost Reduction: Moderators: D. Edenfeld, Intel
Test Economics for Multi-site Test with Modern Cost Reduction TechniquesFull-text access may be available. Sign in or learn about subscription options.pp. 0411
by Erik H. Volkerink, Ajay Khoche, Jochen Rivoir, Klaus D. Hilliges
Session 19: Test-Cost Reduction: Moderators: D. Edenfeld, Intel
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and InterconnectsFull-text access may be available. Sign in or learn about subscription options.pp. 0417
by Krishna Sekar, Sujit Dey
Session 19: Test-Cost Reduction: Moderators: D. Edenfeld, Intel
Useless Memory Allocation in System-on-a-Chip Test: Problems and SolutionsFull-text access may be available. Sign in or learn about subscription options.pp. 0423
by Paul T. Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
Session 20: Oscillation - Based Test: Moderators: B. Kaminska, IMS
Practical Solutions for the Application of the Oscillation-Based-Test: Start-Up and On-Chip EvaluationFull-text access may be available. Sign in or learn about subscription options.pp. 0433
by Diego Vázquez, Gloria Huertas, Gildas Leger, Adoración Rueda, José L. Huertas
Session 20: Oscillation - Based Test: Moderators: B. Kaminska, IMS
Evaluation of the Oscillation-based Test Methodology for Micro-Electro-Mechanical SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 0439
by V. Beroulle, Y. Bertrand, L. Latorre, P. Nouet
Special Session 6: Panel
Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer?Full-text access may be available. Sign in or learn about subscription options.pp. 0445
by Fidel Muradali, Mike Ricchetti, Bart Vermeulen, Bulent Dervisoglu, Bob Gottlieb, Bernd Koenemann, C. J. Clark
Special Session 7: Embedded Tutorial
Challenges in Nanometric Technology Scaling: Trends and ProjectionsFull-text access may be available. Sign in or learn about subscription options.pp. 0447
by Jaume Segura, Vivek De, Ali Keshavarzi
Special Session 8: Panel
SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow?Full-text access may be available. Sign in or learn about subscription options.pp. 0449
by S. Mir, H. Bederr, R. D. Blanton, H. Kerkhoff, H. J. Klim
Special Session 8: Panel
Author IndexFreely available from IEEE.pp. 0451
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