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Proceedings. 21st VLSI Test Symposium, 2003.

Apr. 27 2003 to May 1 2003

Napa Valley, California

ISSN: 1093-0167

ISBN: 0-7695-1924-5

Table of Contents

ForewordFreely available from IEEE.pp. xiv
Organizing CommitteeFreely available from IEEE.pp. xv
Steering CommitteeFreely available from IEEE.pp. xvii
Program CommitteeFreely available from IEEE.pp. xviii
ReviewersFreely available from IEEE.pp. xix
AcknowledgementsFull-text access may be available. Sign in or learn about subscription options.pp. xx
Test Technology Educational Programs: Overview of TutorialsFull-text access may be available. Sign in or learn about subscription options.pp. xxiv
Plenary Session
Keynote AddressFreely available from IEEE.pp. 3
Plenary Session
VTS 2002 Best Panel AwardFreely available from IEEE.pp. 5
Plenary Session
VTS 2002 Best Paper AwardFreely available from IEEE.pp. 6
Session 1A: New Directions in Scan Test
A Reconfigurable Shared Scan-in ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 9
Session 1A: New Directions in Scan Test
Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 15
Session 1A: New Directions in Scan Test
Transition Test Generation using Replicate-and-Reduce Transform for Scan-based DesignsFull-text access may be available. Sign in or learn about subscription options.pp. 22
Session 1B: Outlier Identification & Current Based Test
Use of Multiple IDDQ Test Metrics for Outlier IdentificationFull-text access may be available. Sign in or learn about subscription options.pp. 31
Session 1B: Outlier Identification & Current Based Test
Effectiveness Comparisons of Outlier Screening Methods for Frequency Dependent Defects on Complex ASICsFull-text access may be available. Sign in or learn about subscription options.pp. 39
Session 1B: Outlier Identification & Current Based Test
Effectiveness of I-V Testing in Comparison to IDDq TestsFull-text access may be available. Sign in or learn about subscription options.pp. 47
Session 2A: Advances in Built-In Self-Test - I
High Speed Ring Generators and Compactors of Test DataFull-text access may be available. Sign in or learn about subscription options.pp. 57
Session 2A: Advances in Built-In Self-Test - I
BUILT-IN RESEEDING FOR SERIAL BISTFull-text access may be available. Sign in or learn about subscription options.pp. 63
Session 2A: Advances in Built-In Self-Test - I
BIST RESEEDING WITH VERY FEW SEEDSFull-text access may be available. Sign in or learn about subscription options.pp. 69
Session 2B: Analog and Mixed-Signal Test - I
Ultra Low Cost Analog BIST Using Spectral AnalysisFull-text access may be available. Sign in or learn about subscription options.pp. 77
Session 2B: Analog and Mixed-Signal Test - I
DSP-Based Statistical Self Test of On-Chip ConvertersFull-text access may be available. Sign in or learn about subscription options.pp. 83
Session 2B: Analog and Mixed-Signal Test - I
High Coverage Analog Wafer-Probe Test Design and Co-optimization with Assembled-Package Test to Minimize Overall Test CostFull-text access may be available. Sign in or learn about subscription options.pp. 89
Session 3A: Test Compaction
Analysis and Design of Optimal Combinational CompactorsFull-text access may be available. Sign in or learn about subscription options.pp. 101
Session 3A: Test Compaction
Application of Saluja-Karpovsky Compactors to Test Responses with Many UnknownsFull-text access may be available. Sign in or learn about subscription options.pp. 107
Session 3A: Test Compaction
Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and CompressionFull-text access may be available. Sign in or learn about subscription options.pp. 113
Session 3B: Testing Buses and On-Chip Interconnect
Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential BusesFull-text access may be available. Sign in or learn about subscription options.pp. 121
Session 3B: Testing Buses and On-Chip Interconnect
The Impact of NoC Reuse on the Testing of Core-based SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 128
Session 3B: Testing Buses and On-Chip Interconnect
Automatic Configuration Generation for FPGA Interconnect TestingFull-text access may be available. Sign in or learn about subscription options.pp. 134
Session 4A: Test Challenges in Nanometer Technologies
Threshold Voltage Mismatch (\DeltaVT) Fault ModelingFull-text access may be available. Sign in or learn about subscription options.pp. 145
Session 4A: Test Challenges in Nanometer Technologies
Test Generation for Maximizing Ground Bounce Considering Circuit DelayFull-text access may be available. Sign in or learn about subscription options.pp. 151
Session 4A: Test Challenges in Nanometer Technologies
Testing SoC Interconnects for Signal Integrity Using Boundary ScanFull-text access may be available. Sign in or learn about subscription options.pp. 158
Session 6A: Advanced Test Generation and Fault Simulation Techniques
On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential CircuitFull-text access may be available. Sign in or learn about subscription options.pp. 173
Session 6A: Advanced Test Generation and Fault Simulation Techniques
An Efficient Test Relaxation Technique for Synchronous Sequential CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 179
Session 6A: Advanced Test Generation and Fault Simulation Techniques
Path-Delay Fault Simulation for Circuits with Large Numbers of Paths for Very Large Test SetsFull-text access may be available. Sign in or learn about subscription options.pp. 186
Session 6B: Analog and Mixed-Signal Test - 2
1149.4 Based On-Line Quiescent State Monitoring TechniqueFull-text access may be available. Sign in or learn about subscription options.pp. 197
Session 6B: Analog and Mixed-Signal Test - 2
Measurement of Phase and Frequency Variations in Radio-Frequency SignalsFull-text access may be available. Sign in or learn about subscription options.pp. 203
Session 6B: Analog and Mixed-Signal Test - 2
An Analog Checker with Dynamically Adjustable Error Threshold for Fully Differential CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 209
Session 7A: Test Data Compression
Test Data Compression Using Dictionaries with Fixed-Length IndicesFull-text access may be available. Sign in or learn about subscription options.pp. 219
Session 7A: Test Data Compression
Deterministic Test Vector Decompression in Software Using Linear OperationsFull-text access may be available. Sign in or learn about subscription options.pp. 225
Session 7A: Test Data Compression
Efficient Seed Utilization for Reseeding based CompressionFull-text access may be available. Sign in or learn about subscription options.pp. 232
Session 7B: Memory Testing
Detecting Intra-Word Faults in Word-Oriented MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 241
Session 7B: Memory Testing
Test and Diagnosis of Word-Oriented Multiport MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 248
Session 7B: Memory Testing
Generating Complete and Optimal March Tests for Linked Faults in MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 254
Session 8A: Power Consumption and Test
Energy-Efficient Logic BIST Based on State Correlation AnalysisFull-text access may be available. Sign in or learn about subscription options.pp. 267
Session 8A: Power Consumption and Test
Power Constrained Test Scheduling with Dynamically Varied TAMFull-text access may be available. Sign in or learn about subscription options.pp. 273
Session 8A: Power Consumption and Test
Development of Energy Consumption Ratio TestFull-text access may be available. Sign in or learn about subscription options.pp. 279
Session 8B: Testing Core-Based SoCs
Design for Consecutive Transparency of Cores in System-on-a-ChipFull-text access may be available. Sign in or learn about subscription options.pp. 287
Session 8B: Testing Core-Based SoCs
An Embedded Autonomous Scan-Based Results Analyzer (EARA) for SoC CoresFull-text access may be available. Sign in or learn about subscription options.pp. 293
Session 8B: Testing Core-Based SoCs
Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCsFull-text access may be available. Sign in or learn about subscription options.pp. 299
Special Session 9C: Panel
Embedded Tutorial: Test Consideration for Nanometer Scale CMOS CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 313
Session 10A: System-Level Test Issues
Test Resource Partitioning and Optimization for SOC DesignsFull-text access may be available. Sign in or learn about subscription options.pp. 319
Session 10A: System-Level Test Issues
SOC Test Scheduling Using Simulated AnnealingFull-text access may be available. Sign in or learn about subscription options.pp. 325
Session 10A: System-Level Test Issues
Layered Approach to Designing System Test InterfacesFull-text access may be available. Sign in or learn about subscription options.pp. 331
Session 10B: Diagnosis Techniques
Diagnosis of Delay Defects Using Statistical Timing ModelsFull-text access may be available. Sign in or learn about subscription options.pp. 339
Session 10B: Diagnosis Techniques
Improving Diagnostic Resolution of Delay Faults using Path Delay Fault ModelFull-text access may be available. Sign in or learn about subscription options.pp. 345
Session 10B: Diagnosis Techniques
Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test GenerationFull-text access may be available. Sign in or learn about subscription options.pp. 351
Session 11A: Advances in Built-In Self-Test - 2
BIST-Aided Scan Test - A New Method for Test Cost ReductionFull-text access may be available. Sign in or learn about subscription options.pp. 359
Session 11A: Advances in Built-In Self-Test - 2
Built-In TPG with Designed PhaseshiftsFull-text access may be available. Sign in or learn about subscription options.pp. 365
Session 11A: Advances in Built-In Self-Test - 2
A Test Interface for Built-In Test of Non-Isolated Scanned CoresFull-text access may be available. Sign in or learn about subscription options.pp. 371
Session 11B: Test in the Presence of Bridging Faults
A Circuit Level Fault Model for Resistive Opens and BridgesFull-text access may be available. Sign in or learn about subscription options.pp. 379
Session 11B: Test in the Presence of Bridging Faults
Analyzing Crosstalk in the Presence of Weak Bridge DefectsFull-text access may be available. Sign in or learn about subscription options.pp. 385
Session 11B: Test in the Presence of Bridging Faults
Efficient Implication - Based Untestable Bridge Fault IdentifierFull-text access may be available. Sign in or learn about subscription options.pp. 393
Session 12A: Emerging Circuit Technologies: Test Challenges
Testable Design and Testing of Micro-Electro-Fluidic ArraysFull-text access may be available. Sign in or learn about subscription options.pp. 403
Session 12A: Emerging Circuit Technologies: Test Challenges
Fault Testing for Reversible CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 410
Session 12A: Emerging Circuit Technologies: Test Challenges
Design for Self-Checking and Self-Timed DatapathFull-text access may be available. Sign in or learn about subscription options.pp. 417
Special Session 13C: Panel
Author's IndexFreely available from IEEE.pp. 431
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