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2022 IEEE 40th VLSI Test Symposium (VTS)

April 25 2022 to April 27 2022

San Diego, CA, USA

ISBN: 978-1-6654-1060-1

Table of Contents

Title PageFreely available from IEEE.pp. i-i
Copyright PageFreely available from IEEE.pp. i-i
VTS 2022 ForewordFreely available from IEEE.pp. i-i
VTS 2022 Organizing CommitteeFreely available from IEEE.pp. i-iii
VTS 2022 Steering and Program CommitteesFreely available from IEEE.pp. i-i
Best Paper AwardFreely available from IEEE.pp. i-i
Keynote SpeakersFreely available from IEEE.pp. i-i
SponsorsFreely available from IEEE.pp. i-i
A Hardware-based Evolutionary Algorithm with Multi-Objective Optimization Operators for On-Chip Transient Fault DetectionFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Marcel Merten, Sebastian Huhn, Rolf Drechsler
A Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Aibin Yan, Kuikui Qian, Jie Cui, Ningning Cui, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard
A New Method to Generate Software Test Libraries for In-Field GPU Testing Resorting to High-Level LanguagesFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda
Exploring Model-based Failure Prediction of Passive Bio-electro-mechanical ImplantsFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Daniel Gulick, Yuna Jung, Seunghyun Lee, Sule Ozev, Jennifer Blain Christen
Fault Modeling and Test Generation for Technology-Specific Defects of Skyrmion Logic CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Ziqi Zhou, Ujjwal Guin, Peng Li, Vishwani D. Agrawal
Fault-tolerant Neuromorphic Computing with Functional ATPG for Post-manufacturing Re-calibrationFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Soyed Tuhin Ahmed, Mehdi B. Tahoori
Memristor-Specific Failures: New Verification Methods and Emerging Test ProblemsFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Baishakhi Rani Biswas, Sandeep Gupta
Methods for testing path delay and static faults in RSFQ circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Mingye Li, Fangzhou Wang, Sandeep Gupta
Voltage Tuning for Reliable Computation in Emerging Resistive MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Mahta Mayahinia, Atousa Jafari, Mehdi B. Tahoori
Machine Learning-Based Overkill Reduction through Inter-Test CorrelationFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by D. Neethirajan, V. A. Niranjan, R. Willis, A. Nahar, D. Webster, Y. Makris
Semi-Supervised Root-Cause Analysis with Co-Training for Integrated SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Renjian Pan, Xin Li, Krishnendu Chakrabarty
The Least-Squares Approach to Systematic Error Identification and Calibration in Semiconductor Multisite TestingFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
Balanced Dual-Mask Protection Scheme for GIFT Cipher Against Power AttacksFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Abdullah Aljuffri, Cezar Reinbrecht, Said Hamdioui, Mottaqiallah Taouil, Johanna Sepúlveda
FSMx: Finite State Machine Extraction from Flattened Netlist With Application to SecurityFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Rasheed Kibria, Nusrat Farzana, Farimah Farahmandi, Mark Tehranipoor
Run-Time Hardware Trojan Detection in Analog and Mixed-Signal ICsFull-text access may be available. Sign in or learn about subscription options.pp. 1-8
by Antonios Pavlidis, Eric Faehn, Marie-Minerve Louërat, Haralampos-G. Stratigopoulos
Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel ConfigurationsFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Shi-Xuan Zheng, Chung-Yu Yeh, Kuen-Jong Lee, Chen Wang, Wu-Tung Cheng, Mark Kassab, Janusz Rajski, Sudhakar M. Reddy
FIFO Topology Aware Stalling for Accelerating Coverage Convergence of Stalling RegressionsFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Debarshi Chatterjee, Parth Lathigara, Siddhanth Dhodhi, Chad Parsons
MBIST-based Trim-Search Test Time Reduction for STT-MRAMFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Christopher Münch, Jongsin Yun, Martin Keim, Mehdi B. Tahoori
Exploiting post-silicon debug hardware to improve the fault coverage of Software Test LibrariesFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Riccardo Cantoro, Francesco Garau, Riccardo Masante, Sandro Sartoni, Virendra Singh, Matteo Sonza Reorda
Fast Test Generation for Structurally Similar CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski
Rule Generation for Classifying SLT Failed PartsFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Ho-Chieh Hsu, Cheng-Che Lu, Shih-Wei Wang, Kelly Jones, Kai-Chiang Wu, Mango C.-T. Chao
All Digital Low-Overhead SAR ADC Built-In Self-Test for Fault Detection and DiagnosisFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Mona Ganji, Marampally Saikiran, Degang Chen
Fast RF Mismatch Calibration Using Built-in DetectorsFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Muslum Emir Avci, Sule Ozev, Y.B. Chethan Kumar
Performance Degradation Monitoring for Analog Circuits Using Lightweight Built-in ComponentsFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Bora Bilgic, Sule Ozev
Novel Technique for Manufacturing & In-system Testing of Large Scale SoC using Functional Protocol Based High-Speed I/OFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Amit Pandey, Brendan Tully, Abhijeet Samudra, Ajay Nagarandal, Karthikeyan Natarajan, Rahul Singhal
NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed LinksFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Kaushik Narayanun, Shantanu Sarangi, Francisco Da Silva, Joe Sarmiento, Smbat Tonoyan, Ashwin Chintaluri, Animesh Khare, Milind Sonawane, Ashish Kumar, Anitha Kalva, Alex Hsu, Jayesh Pandey
On-Die Noise Measurement During Automatic Test Equipment (ATE) Testing and In-System-Test (IST)Full-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Seyed Nima Mozaffari, Bonita Bhaskaran, Shantanu Sarangi, Suhas Satheesh, Kuo Lin Fu, Nithin Valentine, P Manikandan, Mahmut Yilmaz
Special Session: Calibrating mismatch in an ISFET with a Floating-GateFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
by Sahil Shah, Jennifer Blain Christen
Special Session: Testing and Characterization for Large-Scale Programmable Analog SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 1-5
by Jennifer Hasler
Special Session: A Testability Practitioner’s Guide to ChipletsFull-text access may be available. Sign in or learn about subscription options.pp. 1-2
by Abram Detofsky
Special Session: Test Impact of Multi-Die PackagesFull-text access may be available. Sign in or learn about subscription options.pp. 1-2
by Vineet Pancholi
Special Session: A Call to Standardize Chip-let Interconnect TestingFull-text access may be available. Sign in or learn about subscription options.pp. 1-3
by Sreejit Chakravarty
Special Session: Closed Chassis Platform Debug of Compute Systems using the Functional Ubiquitous USB Type-C ReceptacleFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
by Sankaran Menon, Rolf Kuehnis
Special Session: Fault-Tolerant Deep Learning: A Hierarchical PerspectiveFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
by Cheng Liu, Zhen Gao, Siting Liu, Xuefei Ning, Huawei Li, Xiaowei Li
Special Session: Fault Criticality Assessment in AI AcceleratorsFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
by Arjun Chaudhuri, Jonti Talukdar, Krishnendu Chakrabarty
Special Session: Effective In-field Testing of Deep Neural Network Hardware AcceleratorsFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
by Shamik Kundu, Suvadeep Banerjee, Arnab Raha, Kanad Basu
Special Session: Towards an Agile Design Methodology for Efficient, Reliable, and Secure ML SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 1-14
by Shail Dave, Alberto Marchisio, Muhammad Abdullah Hanif, Amira Guesmi, Aviral Shrivastava, Ihsen Alouani, Muhammad Shafique
Special Session: STT-MRAMs: Technology, Design and TestFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Anteneh Gebregiorgis, Lizhou Wu, Christopher Münch, Siddharth Rao, Mehdi B. Tahoori, Said Hamdioui
Special Session: On the Reliability of Conventional and Quantum Neural Network HardwareFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
by Mehdi Sadi, Yi He, Yanjing Li, Mahabubul Alam, Satwik Kundu, Swaroop Ghosh, Javad Bahrami, Naghmeh Karimi
Innovative Practices Track: Innovative Analog Circuit Testing TechnologiesFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Chris Mangelsdorf, Manasa Madhvaraj, Salvador Mir, Manuel Barragan, Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Yujie Zhao, Jianglin Wei, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa
Innovative Practices Track: High Speed Test FabricFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Bala Tarun Nelapatla, Rahul Singhal, Michael Daub, Zoran Stanojevics
Innovative Practices Track: Next Generation Test StandardsFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Arani Sinha
Innovative Practices Track: New Methods for System Level Test of Image Projection and Radar VLSI SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Rubin A. Parekhji
Innovative Practices Track: Test of 3D ICs & ChipletsFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Sandeep Kumar Goel, Sandeep Pendharkar, Chunsheng Liu
Innovative Practices Track: Silent Data ErrorsFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Arani Sinha
Innovative Practices Track: What’s Next for Automotive: Where and How to Improve Field Test and Enhance SoC SafetyFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Minqiang Peng, Youfa Wu, Jialiang Li, Alex Yu, Grigor Tshagharyan, Costas Argyrides, Vilas Sridharan, Gurgen Harutyunyan, Yervant Zorian, Nilanjan Mukherjee
Innovation Practices Track: Security in Test and Test for SecurityFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Gang Qu, Benjamin Tan, Kuheli Pratihar, Debdeep Mukhopadhyay, Ramesh Karri
Innovation Practices Track: Silicon Telemetry for DependabilityFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Fei Su, Stephen Crosher, Andrea Matteucci, Yuwen Zou
Innovative Practices Track: Novel Methods for Validation and TestFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Nitin Chaudhary
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