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Proceedings
VTSA
VTSA 1991
Generate Citations
1991 International Symposium on VLSI Technology, Systems, and Applications
May 22 1991 to May 24 1991
Taipei, Taiwan
Table of Contents
High-density ASICs with a three-dimensional CMOS process
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pp. 297,298,299,300
by
G. Roos
,
B. Hofflinger
,
M. Schubert
,
R. Zingg
An analytical model of threshold voltage and subthreshold swing for ultra-thin-film SOI MOSFETs
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pp. 293,294,295,296
by
Heng Tien Chen
,
Ruey Shing Huang
A new model on the mechanisms of high-frequency AC hot-carrier effects in MOS devices
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pp. 288,289,290,291,292
by
Chung-Yu Wu
,
Charng-Feng Hsu
,
Ying-Che Wu
A new MOSFET hot carrier model in SPICE feasible for VLSI reliability analysis
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pp. 283,284,285,286,287
by
S.S. Chung
,
P.-C. Hsu
,
J.-S. Lee
The improvement of I-V characteristics curve fitting by the modification of SPICE model-level 3
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pp. 278,279,280,281,282
by
Chung-Zen Chen
Depletion region formation at low temperatures
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pp. 274,275,276,277
by
C.R. Viswanathan
,
R. Divakaruni
,
V. Prabhakar
Advanced bipolar technology for the 1990s
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pp. 269,270,271,272,273
by
J.Y.-C. Sun
,
J.H. Comfort
,
J. Warnock
,
J.D. Cressler
,
G. Patton
,
J.M.C. Stork
,
J. Burghartz
,
D. Harame
,
E. Crabbe
,
P.-F. Lu
,
M. Arienzo
,
B. Meyerson
Stacked capacitor cells for 64 MDRAM
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pp. 264,265,266,267,268
by
T. Matsukawa
,
T. Nakano
A 13-bit analog interface for microprocessor-based systems
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pp. 260,261,262,263
by
J.-Y. Michel
,
H. Mohajeri
,
Chanh Vi Tran
A single chip mixed digital/analog signal processor in 1.2 mu CMOS interfacing 4 analog subscriber lines to the PCM digital System 12 exchange
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pp. 257,258,259
by
J. Sevenhans
,
D. Haspeslagh
,
A. Delarbre
,
L. Kiss
,
E. Moerman
A transceiver for 800 kb/s full-duplex transmission over digital subscriber loops using a custom VLSI adaptive filter processor
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pp. 252,253,254,255,256
by
B.A. Itri
,
R.H. Brackert
,
H.T. Nicholas
,
H. Samueli
An instruction set for a programmable signal processor dedicated to Viterbi detection
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pp. 247,248,249,250,251
by
Hui-ling Lou
,
J.M. Cioffi
A design and implementation of multi-dimensional Y-C separation filters for NTSC TV signals
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pp. 242,243,244,245,246
by
K. Ashizawa
,
T. Yoshida
,
A. Nishihara
A video buffer controller design for HDTV/BISDN system
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pp. 237,238,239,240,241
by
Shyi-Ching Liau
Experimental VLSI for HDTV and broadband fiber networks
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pp. 232,233,234,235,236
by
J.A. Bellisio
,
R.R. Cordell
HDTV in 1990s
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pp. 227,228,229,230,231
by
K. Ogi
,
H. Yamada
A novel method to characterize and screen mobile ion contaminated nonvolatile memory products
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pp. 224,225,226
by
F. Shone
,
H. Liou
,
C. Pan
,
B. Woo
,
M. Holler
Effects of the field-edge transistor on SOI MOSFETs
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pp. 219,220,221,222,223
by
Jian Chen
,
Ping Keung Ko
,
Chenming Hu
,
R. Solomon
,
Tung-Yi Chan
Implications of waveform and thickness dependence of SiO/sub 2/ breakdown on accelerated testing
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pp. 214,215,216,217,218
by
E. Rosenbaum
,
R. Moazzami
,
C. Hu
Characterization of thin oxide damage during aluminum etching and photoresist ashing processes
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pp. 210,211,212,213
by
H. Shin
,
C.-C. King
,
R. Moazzami
,
T. Horiuchi
,
C. Hu
Suppression of both sidewall injection and hot-carrier effects using laterally graded emitter in bipolar transistors
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pp. 205,206,207,208,209
by
Tzuen-Hsi Huang
,
Ming-Jer Chen
,
Ching-Yuan Wu
Determination of MOSFET's channel doping profile right up to SiO/sub 2//Si interface
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pp. 201,202,203,204
by
Pole-Shang Lin
,
Chih-Hsien Wang
Lateral distribution of hot-carrier-induced oxide charge and interface traps in MOSFET's
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pp. 196,197,198,199,200
by
W. Chen
,
A. Balasinski
,
T.-P. Ma
Simulation of P- and N-MOSFET hot-carrier degradation in CMOS circuits
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pp. 191,192,193,194,195
by
P.M. Lee
,
T. Garfinkel
,
P.K. Ko
,
C. Hu
VLSI/ULSI research methodology in the US and Japan
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pp. 187,188,189,190
by
Y. Nishi
GEAR: a general area router using planning approach
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pp. 182,183,184,185,186
by
Yuh-Lin Chen
,
Sao-Jie Chen
,
Chia-Chun Tsai
,
Yu-Hen Hu
VLSI routing methodology for quadrupole metal sea-of-cells design
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pp. 177,178,179,180,181
by
H.H. Chen
,
C.K. Wong
Using timed Boolean algebra to solve false path problem in timing analysis
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pp. 172,173,174,175,176
by
Shiang-Tang Huang
,
Tai-Ming Parng
,
Jyuo-Ming Shyu
Evaluation driven layout synthesis
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pp. 167,168,169,170,171
by
A.C.-H. Wu
,
D.D. Gajski
,
G.-D. Chen
Circuit optimization techniques in DROID
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pp. 162,163,164,165,166
by
H.Y. Chen
,
S. Agarwala
,
S. Dutta
,
D. Matzke
,
P. Bosshart
,
S. Lusky
,
P. Kollaritsch
Simultaneous topology selection and timing assignment for LSI circuits based on semi-analytical delay-area expression
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pp. 157,158,159,160,161
by
Zhi-jian Dai
,
K. Asada
Transient sensitivity computation for waveform relaxation-based timing simulation
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pp. 152,153,154,155,156
by
Chun-Jung Chen
,
Jyuo-Min Shyu
,
Wu-Shiung Feng
An integrated technology CAD environment
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pp. 147,148,149,150,151
by
F. Fasching
,
C. Fischer
,
S. Halama
,
H. Pimingstorfer
,
H. Read
,
S. Selberherr
,
H. Stippel
,
P. Verhas
,
K. Wimmer
Approaches to high pin count and high power surface mount packages
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pp. 141,142,143,144,145,146
by
P. Lin
,
M. McShane
The advanced improvement of PN mesa junction diode prepared by silicon-wafer direct bonding
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pp. 136,137,138,139,140
by
Ching-Fa Yeh
,
Shyang Hwang-Leu
,
Jui-I Tsai
Color CCD image sensor
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pp. 126,127,128,129,130
by
Yeong-Wen Daih
,
Cheng-Chung Chien
,
Dar-Chang Juang
,
Tzer-Yaa Bin
,
Ching-Yi Hsu
,
Chang-Daw Wu
,
Yee-Lu Zhaog
,
Men-Fen Ho
,
Ming-Hsien Cheng
,
Geun-Pin Yang
,
Yau-Feng Luo
,
Chung-Hsien Horng
Photo-excited dry cleaning for ULSI devices
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pp. 122,123,124,125
by
Y. Sato
,
R. Sugino
,
M. Okuno
,
N. Kikuchi
,
J. Teramae
,
A. Ogawa
,
S. Hijiya
,
T. Ito
A deep-submicrometer raised source/drain LDD structure fabricated using hot-wall epitaxy
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pp. 117,118,119,120,121
by
J.E. Moon
,
C. Galewski
,
T. Garfinkel
,
M. Wong
,
W.G. Oldham
,
P.K. Ko
,
C. Hu
Double spacer technique for titanium self-aligned silicidation technology
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pp. 113,114,115,116
by
W.D. Su
,
S.W. Chang
Al-plug stacked contact/via process for deep submicron CMOS multilayer metal technology
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pp. 109,110,111,112
by
F.T. Liou
,
F.S. Chen
,
G.A. Dixit
,
M. Zamanian
,
G. DeSanti
Suppression of boron penetration in BF/sub 2//sup +/-implanted polysilicon gated p-MOSFETs with reoxidized nitrided gate oxides
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pp. 104,105,106,107,108
by
G.Q. Lo
,
W. Ting
,
D.L. Kwong
Cooling for high heat flux VLSI systems
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pp. 99,100,101,102
by
R.C. Jaeger
,
J.S. Goodling
A 32 bit microcontroller with an embedded flash EEPROM
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pp. 94,95,96,97,98
by
C. Kuo
,
M. Weidner
,
T. Toms
,
H. Choe
,
A. Harwood
,
R. Jones
,
J. Jelemensky
,
Ko-Min Chang
Identification of DRAM sense amplifier imbalance using hot carrier evaluation
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pp. 90,91,92,93
by
S. Aur
,
C. Duvvury
,
H. McAdams
,
C. Perrin
Circuit techniques for a wide world I/O path 64 Meg DRAM
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pp. 87,88,89
by
K. Komatsuzaki
,
S. Sukegawa
,
K. Fung
,
T. Inui
,
T. Suzuki
,
R. Rountree
,
J. You
,
B. Borchers
,
T. Komatsuzaki
,
H. Shichijo
,
H. Tran
,
D. Scott
A subnanosecond clamped-bit-line sense amplifier for 1T dynamic RAMs
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pp. 82-86
by
T.N. Blalock
,
R.C. Jaeger
A coded block adaptive neural network structure for pattern recognition VLSI
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pp. 79,80,81
by
J.B. Kuo
,
Y.K. Chen
,
Y.H. Lu
,
W.C. Mao
Multiprocessor-based video motion detection using adaptive neural systems
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pp. 74,75,76,77,78
by
J.C. Lee
,
B.J. Sheu
,
C.F. Chang
,
R. Chellappa
A scheme for implementation of neural networks with replicated receptive fields
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pp. 69,70,71,72,73
by
M. Chuang
A multichip analog neural network
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pp. 64,65,66,67,68
by
J. Van der Spiegel
,
P. Mueller
,
V. Agami
,
P. Aziz
,
D. Blackman
,
P. Chance
,
A. Choudhury
,
C. Donham
,
R. Etienne-Cummings
,
L. Jones
,
J. Kim
,
P. Kinget
,
M. Massa
,
W. von Koch
,
J. Xin
DARPA artificial neural network technology program
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pp. 61,62,63
by
B.L. Yoon
Misfit stress in p/p+ epitaxial silicon wafers: effect and elimination
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pp. 57,58,59,60
by
W. Lin
,
D.W. Hill
,
C.L. Paulnack
,
M.J. Kelly
A high quality stacked thermal/LPCVD gate oxide for ULSI
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pp. 52,53,54,55,56
by
R. Moazzami
,
C. Hu
Superior performance and reliability of MOSFETs with ultrathin gate oxides prepared by conventional furnace oxidation of Si in pure N/sub 2/O ambient
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pp. 47,48,49,50,51
by
W. Ting
,
G.Q. Lo
,
J. Ahn
,
D.L. Kwong
Pits reduction for poly Buffer LOCOS in VLSI fabrication
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pp. 43,44,45,46
by
W.D. Su
,
P.P.J. Lee
,
C.C. Chang
,
C.H. Cheng
LOCOS-based isolation for 0.5 mu m device with PLD (polysilicon-spacered lateral diffusion) technology
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pp. 38,39,40,41,42
by
W.S. Paik
,
T.Y. Jang
,
W.M. Park
,
W.T. Choi
,
S.G. Yang
,
J.H. Shin
,
Y.P. Kim
,
K.S. Oh
,
O.H. Kwon
,
Y.E. Park
Electron beam direct writing systems for 64 Mbit DRAM and beyond
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pp. 33,34,35,36,37
by
K. Nakamura
,
N. Saitou
Selective silylation and plasma patterning of photoresist in submicron lithography
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pp. 28,29,30,31,32
by
B. Chen
,
T.P. Ma
Advanced i-line lithography for 0.5 mu m CMOS technology
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pp. 22,23,24,25,26,27
by
T. Yang
,
C.C. Fu
,
T.M. Wolf
,
T.E. Adams
,
J.G. Costigan
,
J.L. Ryan
,
D.E. Schrope
,
D.R. Stone
,
J.D. Cuthbert
Quarter- and sub-quarter-micron optical lithography
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pp. 16,17,18,19,20,21
by
B.J. Lin
Gigascale integration (GSI) beyond 2001
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pp. 12,13,14,15
by
J.D. Meindl
The European microelectronics industry and its challenge for the nineties
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pp. 8,9,10,11
by
H. Friedrich
,
F.S. Becker
Home electronics in the 1990s
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pp. 1,2,3,4,5,6
by
K. Shoda
1991 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No. 91TH0368-1)
Freely available from IEEE.
pp. 0_1-0_1
Gallium arsenide and silicon for optical electronics: applications and technology trade-offs
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pp. 389,390,391,392,393
by
R.G. Swartz
SCOPE-a simultaneous contact and planarization etch process for low-cost high-performance CMOS applications
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pp. 385,386,387,388
by
K.K. Young
,
W. Uesato
,
H.K. Hu
,
P.E. Riley
,
S.S. Peng
,
K.Y. Chiu
Large-area MOVPE growth for HEMT LSI
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pp. 380,381,382,383,384
by
T. Ohori
,
N. Tomesakai
,
M. Suzuki
,
S. Notomi
,
J. Komeno
Characteristics of vertical p-channel MOSFETs for high density circuit application
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pp. 376,377,378,379
by
D.S. Wen
,
W.H. Chang
,
T.V. Rajeevakumar
,
G.B. Bronner
,
P.A. McFarland
,
Y. Lii
,
T.C. Chen
,
F.L. Pesavento
,
M.P. Manny
,
W. Hwang
,
S.H. Dhong
Peeling-free tungsten polycide process and its application in DRAM fabrication
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pp. 371,372,373,374,375
by
C.S. Yoo
,
M.S. Lin
,
T.H. Lin
,
L.J. IJzendoorn
A 64 Mbit DRAM trench capacitor cell with field-plate isolation
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pp. 366,367,368,369,370
by
C.W. Teng
,
Y. Okumoto
,
J. Liu
,
Ih-Chin Chen
,
K. Yuhara
,
Y. Yoneoka
A 0.5 mu m diode load 4 Mb SRAM technology using double-level Al plug metal process
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pp. 362,363,364,365
by
R. Sundaresan
,
C.C. Wei
,
M. Zamanian
,
F.S. Chen
,
R.O. Miller
,
R.L. Hodges
,
W. Gaskins
,
P. Sagarwala
,
L. Nguyen
,
J. Huang
,
C. Spinner
,
G.S. Stagaman
,
L. Lu
,
Y.S. Lin
,
F. Bryant
,
F.T. Liou
A twin-tub CMOS using self-aligned channel-stop in conjunction with poly-buffer LOCOS for 1M/4M SRAM application
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pp. 358,359,360,361
by
M.-L. Chen
,
W. Juengling
,
S.J. Hillenius
,
T.S. Yang
,
C.C. Fu
,
D.P. Favreau
,
R. Powell
Low power, low voltage memories for portable electronics
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pp. 354,355,356,357
by
O. Minato
,
K. Ishibashi
DRAM technology trend and prospect
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pp. 349,350,351,352,353
by
H. Shichijo
High performance CMOS VLSI chip set for synchronous optical transmission systems
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pp. 344,345,346,347,348
by
T.C. Poon
,
A.J.-H. Lee
,
S.S. Austin
,
J.P. Kunz
ARES-architecture reinforcing superscalar
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pp. 338,339,340,341,342,343
by
Yuh-Haur Lin
,
Feipei Lai
,
Meng-Chou Chang
CMOS cell base implementation of the SPARC architecture
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pp. 334,335,336,337
by
S.T. Wang
,
S.J. Lai
,
J. Chou
,
H.Y. Tarn
,
C.C. Chang
,
S.W. Tung
,
J.Y. Ray
,
J.Y. Kuo
,
L.M. Yang
Modeling and design analysis of a workstation LAN server
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pp. 329,330,331,332,333
by
F.W. Shih
,
Jyh-Herng Chow
,
Shauchi Ong
,
Limin Hu
TRAMPS/2: trace referenced analysis model of the personal system/2
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pp. 322,323,324,325,326,327,328
by
D.M. Wronski
,
T.B. Genduso
,
C. Moy
The designs of two-level pipelined systolic arrays for recursive digital filters with maximum throughput rate
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pp. 317,318,319,320,321
by
Shih-Chieh Wen
,
Chi-Min Liu
,
Chein-Wei Jen
A systolic architecture for computing inverses in finite fields GF (2/sup m/)
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pp. 312,313,314,315,316
by
Chin-Liang Wang
,
Jung-Lung Lin
The design of two-dimensional FIR and IIR filter architectures for HDTV signal processing
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pp. 307,308,309,310,311
by
Hwan-Rei Lee
,
Chein-Wei Jen
Wafer-scale systolic array for adaptive antenna processing
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pp. 304,305,306
by
C.M. Rader
Channel mobility of GeSi quantum-well P-MOSFETs
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pp. 301,302,303
by
D.K. Nayak
,
J.C.S. Woo
,
J.S. Park
,
K.L. Wang
,
K.P. MacWilliams
Advanced bipolar circuits-a perspective
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pp. 394,395,396,397
by
C.T. Chuang
A new type of curvature-compensated CMOS bandgap voltage references
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pp. 398,399,400,401,402
by
Shu-Yuan Chin
,
Chung-Yu Wu
Accurate parametric interconnect modeling for high frequency LSI/VLSI circuits and systems
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pp. 403,404,405,406,407,408
by
C.G. Lin-Hendel
,
J. Loos
,
K.K. Thornber
Design of pseudoexhaustive testable PLA with low overhead
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pp. 409,410,411,412,413
by
Wen-Zen Shen
,
Gwo-Haur Hwang
,
Wen-Jun Hsu
,
Yun-Jung Jan
A new pseudo-exhaustive test method
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pp. 414,415,416,417,418
by
Jhing-Fa Wang
,
Wei-Lun Wang
,
Tzyy-Kuen Tien
Parallel sequence fault simulation for synchronous sequential circuits
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pp. 419,420,421,422,423
by
Chen-Pin Kung
,
Chen-Shang Lin
An event-driven incremental timing fault simulator
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pp. 424,425,426,427
by
Shyh-Jye Jou
,
Wen-Zen Shen
,
Shwu-Huey Chiou
Extraction of defect characteristics for yield estimation using the double bridge test structure
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pp. 428,429,430,431,432
by
J.B. Khare
,
B.J. Daniels
,
D.M. Campbell
,
M.E. Thomas
,
W. Maly
On integrating control algorithms for buffer management and concurrency for parallel transaction processing systems
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pp. 433,434,435,436,437,438
by
Shiwei Wang
,
Y. Hsu
Showing 93 out of 93