Dr. Edward B. Eichelberger is an IBM Fellow and Manager of Advances VLSI Technology and Testing at the IBM Mid-Hudson Valley Laboratories in Kingston. He has worked and published in the areas of VLSI chip design, circuit design, design automation and design for testability.
Edward B. Eichelberger received his B.S. in electrical engineering from Lehigh University in 1956. He joined IBM after graduation to work in solid state circuit design at the Endicott Product Development Laboratory. In 1959, he began graduate study at Princeton University under the IBM Resident Graduate Study Program. While at Princeton, he worked in the field of switching theory and received his M.A. and Ph.D. degrees in electrical engineering in 1963. Dr. Eichelberger then resumed his duties at the laboratory in Endicott. At the time he published his paper on hazard detection in combinational and sequential circuits in 1965, he was serving as the manager of scientific computation, where he no doubt observed the large amounts of computer time consumed for simulation and test generation.
Taking a more active role in influencing the design of circuits, he developed the concepts of level-sensitive scan design. It was then necessary to convince designers and their mangers that LSI required new techniques for testing and these must be designed from the beginning. Teaming up with Tom Williams the concepts were ultimately accepted.
Since 1977, he has managed various custom design VLSI projects in both FET and bipolar technologies. Dr. Eichelberger has published extensively and holds 16 U.S. patents, four of which are joint with Dr. Williams.
Among his honors, Dr. Eichelberger was elected an IEEE Fellow in 1986. He received an IBM Outstanding Contribution Award for the “Level sensitive Scan Design” (LSSD) technique in 1973, and also an Outstanding Innovation Award for Weighted Random Patterns.
