Abstract
Modern devices often include several embedded instruments, such as BISTs, sensors, and other analogcomponents. New standards, such as IEEE Std. 1687, providevehicles to access these instruments. In approaches based onreconfigurable scan networks, instruments are coupled withscan registers, connected into chains and interleaved withreconfigurable multiplexers, permitting a selective access todifferent parts of the chain. A similar scenario is also supportedby IEEE Std. 1149.1-2013, where a test data register can beconstructed as a chain of multiple segments, some of which canbe excluded or mutually selected. The test of permanent faultsaffecting a reconfigurable scan network requires to shift testpatterns throughout a certain number of network configurations. This paper presents a method to select the list of configurationsneeded to apply the complete test set in the minimum amount ofclock cycles. The method is based on a graph representation ofthe problem. Experimental results on some benchmark networksare provided, together with a comparison with other approachesbased on heuristics. The provided results can be effectively usedto evaluate the test time of sub-optimal approaches.