Abstract
Design, production and operation of modern system-on-chips rely on integrated instruments, which range from simple sensors to complex debug interfaces and design-for-test (DfT) structures. Reconfigurable scan networks (RSNs) as defined in IEEE Std. 1687-2014 provide an efficient access mechanism to such instruments. It is essential to test the access mechanism itself before it can be used for test, diagnosis, validation, calibration or runtime monitoring. Realistic fault mechanisms in RSNs are hard to test due to their high sequential depth and limited controllability and observability via serial scan ports.We present a novel low-cost DfT modification specifically designed for RSNs that enhances the observability of shadow registers. Furthermore, we present different test methods for stuck-at and more realistic gate-level fault models like flip-flop-internal and bridge faults. Experimental results demonstrate the effectiveness of the presented DfT modification and test methods.