A resistorless current reference source for 65 nm CMOS technology with low sensitivity to process, supply voltage and temperature variations

Michał Łukaszewicz; Tomasz Borejko; Witold A. Pleskacz

doi:10.1109/DDECS.2011.5783051

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

A resistorless current reference source for 65 nm CMOS technology with low sensitivity to process, supply voltage and temperature variations

Year: 2011, Pages: 75-79

DOI Bookmark: 10.1109/DDECS.2011.5783051

Authors

Michał Łukaszewicz, Institute of Microelectronics & Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warszawa, POLAND
Tomasz Borejko, Institute of Microelectronics & Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warszawa, POLAND
Witold A. Pleskacz, Institute of Microelectronics & Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warszawa, POLAND

Abstract

A reistorless current reference source, e.g. for fast communication interfaces, has been described. Addition of currents with opposite temperature coefficient (PTC and NTC) and body effect have been used to temperature compensation. Cascode structures have been used to improve the power supply rejection ratio. The reference current source has been designed in a GLOBALFOUNDRIES 65 nm technology. The presented circuit achieves 55 ppm/°C temperature coefficient over range of -40°C to 125°C. Reference current susceptibility to process parameters variation is ±3 %. The power supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz is lower than -127 dB and -103 dB, respectively.

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A resistorless current reference source for 65 nm CMOS technology with low sensitivity to process, supply voltage and temperature variations

Authors

Abstract

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