Abstract
According to Moore's Law, the number of transistors on a single chip doubles every two years, allowing tens or even hundreds of cores to be integrated. As multi-cores communicate with memory, the underlying Network-on-Chip (NoC) experiences different stress levels due to asymmetric traffic patterns and complex routing algorithms. Unfortunately, the growth in the number of transistors in NoCs will significantly impact both reliability (physical failures) and aging (uneven utilization) due to the increasing effects of Electromigration (EM), Hot carrier injection (HCI) and Negative Bias Temperature Instability (NBTI). In this paper, we propose a novel in-flight, adaptive, routing algorithm to reduce the accumulation of EM, HCI, and NBTI effects on the lifetime of NoC. The proposed routing algorithm is based on a new metric called Packet-Per-Port (P3) which equalizes the stress throughout the network. The net impact is that the network components such as the links and the routers will age evenly and thereby improve NoC reliability and maximize the lifetime of the chip. Our results indicated that for Splash-2 traces, we observe 7.3% to 13.7% energy per bit reduction and up to 6.23% improvement in the transistor reliability when compared to Dimensional Order Routing (DOR) on 8×8 mesh.