Short destabilizing paths in timing verification

R.P. Llopis; L.R. Xirgo; J.C. Bordoll

doi:10.1109/ICCD.1994.331879

Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors

Short destabilizing paths in timing verification

Year: 1994, Pages: 160,161,162,163

DOI Bookmark: 10.1109/ICCD.1994.331879

Authors

R.P. Llopis, Centro Nacional de Microelectronica, Univ. Autonoma de Barcelona, Spain
L.R. Xirgo, Centro Nacional de Microelectronica, Univ. Autonoma de Barcelona, Spain
J.C. Bordoll, Centro Nacional de Microelectronica, Univ. Autonoma de Barcelona, Spain

Abstract

Designing an optimal clocking scheme for a sequential circuit requires accurate knowledge of the delay of its longest sensitizable and of its shortest destabilizing path. However, there is a large imbalance in the research effort spent on both types of paths. This paper tries to compensate this imbalance, by presenting a new destabilizing criterion, for which it will be proved that it leads to correct optimal clocking schemes. Furthermore, this paper results in clocking schemes which are tighter in comparison with those presented in literature.<>

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Short destabilizing paths in timing verification

Authors

Abstract

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