Abstract
Stochastic computing (SC) with its small area and power footprint is a prime candidate for realizing neural networks (NNs) in heavily resource-restricted devices, such as near-sensor computing systems. Complete SCNNs encompassing all network layers have mostly been simulated in software, or synthesized without consideration of potential area limitations. In this work, we present a full FPGA implementation of a complete SCNN for image classification under tight resource constraints. All computational operations of the NN are performed on FPGA primitives. Furthermore, no DSPs and no onboard CPU is required for the computation. Our system operates at 60MHz and can classify an input image within approximately 6ms. Moreover, our basic SC and memory components can be flexibly combined to cover a large variety of NN structures.