Abstract
The design and integration challenges for SOCs include DFT for test integration to meet the test quality and test cost goals. This work describes the DFT implementation on TNETD7300, a single chip ADSL modem SOC with analog and digital sub-systems, IP cores and embedded memories, to address several test optimisation requirements, including scan architecture support for high-end and low-cost testers, concurrent test of digital logic with analog functions, at-speed testing for logic operating in different clock domains and clock frequencies, testing non-homogeneous IP cores together, configurable memory BIST operation, static and dynamic burn-in, and a comprehensive set of SOC test modes to support these operations. These techniques have significantly influenced the silicon test of this device, and have also influenced the design and test methodology adopted in other similar designs in Texas Instruments.