Abstract
The PowerPC 603 microprocessor is designed for low power, low cost computing applications. A RAM built-in-self-test (BIST) implementation tests the split 8k instruction and data caches and the tag arrays. The design is constrained by the need to minimize area overhead while providing high test coverage and rapid at-speed testing. The solution encompasses a novel state machine design built using logic synthesis tools. This paper presents the RAM BIST design implemented on the PowerPC 603 microprocessor.