Testing CMOS logic gates for: realistic shorts

B. Chess; A. Freitas; F.J. Ferguson; T. Larrabee

doi:10.1109/TEST.1994.527981

Proceedings of International Test Conference

Testing CMOS logic gates for: realistic shorts

Year: 1994, Pages: 395,396,397,398,399,400,401,402

DOI Bookmark: 10.1109/TEST.1994.527981

Authors

B. Chess, Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
A. Freitas, Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
F.J. Ferguson, Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
T. Larrabee, Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA

Abstract

It is assumed that tests generated using the single stuck-at fault model will implicitly detect the vast majority of fault-causing defects within logic elements. This may not be the case. In this paper we characterize the possible shorts in the combinational cells in a standard cell library. The characterization includes errors on the cell outputs, errors on the cell inputs, and excessive quiescent current. The characterization provides input vectors to stimulate these errors. After characterizing the faults that occur due to possible electrical shorts, we compare the coverage of the logic faults using a single stuck-at test set and tests developed specifically to detect these shorts. We discuss the effectiveness of I/sub DDQ/ testing for these faults.

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Testing CMOS logic gates for: realistic shorts

Authors

Abstract

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