Abstract
It is forecasted that by 2003, a large number of applications will use CMOS technology for RF system-on-chip, such as remote control, radio modems, home system automation, etc. For example, in the home system automation, the concept is to replace the data cable between appliances by wireless link centered at 2.4GHz, with a range of approximately 8m. The reliability of the components used in these applications is, therefore, obviously very important. Further, rapid progress in Silicon technologies results in additional set of constraints (mostly) and occasionally beneficial solutions. Harnessing the reliability without sacrificing the performance in the deep sub-micron CMOS technology is of major emphasis in the semiconductor industry. In this tutorial, the ESD reliability challenges faced from technology generations, as well as, circuit design point of view are reviewed. After a brief introduction on the fundamental of electrostatic discharge, detailed description on the ESD testing and models are presented. This intended to provide an in-depth insight into the ESD models, physical and circuit equivalents, relevant international testing standards and procedures for beginners and experts. Novel testing methods for effective device characterization/parameter extraction for circuit level simulation is highlighted. This is a key learning step for circuit designers as such a inter-disciplinary topic is of high interest since it can link the physical failures to circuit simulation. This is followed by a review on the basic on-chip ESD protection building blocks in terms of stand-alone devices and integrated protection circuit schemes. In this section, the ESD specific behavior and application of various standard protection devices such as resistors, diodes, grounded gate nMOST, etc. are explained. Influence of the silicon process and scaling is discussed along with device optimization specific for ESD performance.