Abstract
Clock generation is an extremely important part of any electronic system. At present Crystal oscillator is the most stable and reliable clock generation technique used as clock generation for any type of SoC. But this solution is very expensive and inconvenient for chip integration. Second option can be PLL based clock generation technique. Again PLL based techniques uses huge silicon area and high on-chip power. Further PLL based clocks need a reference clock for locking system. So we need a solution which can provide a stable clock against process, temperature and supply variations. CMOS Ring Oscillator provides a ready solution, but the biggest challenge with this kind of circuit is to achieve stable clock with temperature, process and supply voltage variations. This paper describes a symmetric oscillator structure, which provides an on-chip compensated clock against process, temperature and supply variations. This architecture is not one to one replacement of crystal oscillator or PLL but is very useful for many applications like on-chip charge-pump or DC-DC converters, clock required for modify pulse in Phase Change Memory etc. The oscillator is designed in BCD9S (110nm) process, to produce a stable frequency of 20 MHz, within a temperature range of -40 to 160oC and supply varying from 3V to 5.5V. The variation of frequency is within ±4.5% range and the circuit overall consumes an average current of 68μA.