Abstract
This paper presents the design of an inductorless low power differential Low Noise Amplier (LNA) for multi-standard radio applications between 0.2-3.2 GHz. Conventionally, the low power shunt-feedback based LNA noise performance suffers due to the low intrinsic gm of MOS transistors. A single stage differential shunt-feedback LNA which incorporates both, Gm boosting and current-reuse technique is proposed to overcome the noise performance degradation in low power designs. A detailed analysis of the conventional inductorless shunt-feedback based LNA along with the proposed technique is provided. It provides a good trade-off between different performance parameters after sizing and biasing optimization under ultra low power design constraint. The proposed technique is implemented in 65 nm CMOS technology and occupies an active area of 0.25 mm2. It exhibits a power gain of 13.5 dB with 1.6 dB NF while dissipating only 0.6 mW power.