A 10 Gb/s On-chip Jitter Measurement Circuit Based on Transition Region Scanning Method

This paper proposes a 10-Gb/s On-chip jitter measurement (OCJM) circuit to measure peak-to-peak jitter of data/clock signals in high-speed transceivers and system-on-chips (SOCs). The peak-to-peak jitter measurement circuit is based on a novel transition region scanning (TRS) technique. The maximum transition region (TR) width of data/clock first converts to an equivalent pulse, and subsequently, the pulse width is scanned by a slowly moving clock edge to construct peak-to-peak jitter width. The peak-to-peak jitter width finally converts to an equivalent peak-to-peak voltage which gives the on-chip jitter information in the form of voltage. The proposed OCJM circuit uses a sub-rate (sub-multiple of data/clock frequency to be measured) clock signal and a voltage-controlled delay line (VCDL) circuit to carry out the scanning process of the TR width of jittery data/clock. The time-to-voltage (TVC) circuit is used for converting timing jitter to voltage, and the peak detector (PD) circuit is responsible for giving the peak voltage corresponding to the peak-to-peak jitter. This OCJM architecture is capable of characterizing the jitter performance at any arbitrary node inside the chip. Implementation wise this OCJM circuit is a fully on-chip and complete analog solution. A test chip has been designed and fabricated using 65 nm CMOS technology with a core silicon area of $910 ~\mu \mathrm{m} \times 300 ~\mu \textbf{m}$. The complete architecture consumes 11.4-mW at a 10-Gb/s data rate. The measurement result confirms that the architecture is working fine as the output voltage varies proportionally with the peak-to-peak jitter of target jittery data or clock signal.