Abstract
Scaling of the MOSFET feature size, with an advance in technology, leads to a significant increase in the static power of mobile or IoT device system-on-chip (SoC), so a specialized retention mode, with voltage lowering, is used. Rail-to- Rail (Vret) supply during retention mode should be above the minimum (Vret-min) to guarantee bit-cell (BC) data integrity of Static Memory (SRAM). Lower temperatures like −40°C or corner lots are the worst conditions for Vret-min [1], and the worst-case design approach is not efficient for nominal or fast corners. An adaptive regulation scheme [2] is one way of approaching this issue, but the monitor to track the statistically (local variation) worst BC is difficult to design. We present a closed-loop system (CLS) with temperature modulation and a digital signal bus (RM) controlled “reference generator” to adapt the temperature and process, respectively, without relying on monitors. The system is built-in to the memory and can be programmed differently for corners by RM with information from process centering. Implementation with single-port high-density 0.242um2 BC (HD242) in 40nm technology shows leakage reduction of ~77% and ~62% in comparison to “no retention” and “worst-case design approach” respectively at the typical lot and 25 °C temperature.