Abstract
We investigate the classical problem of conformance checking (CC) for non-scan synchronous sequential machines from a new perspective of “design-for-verifiability” utilizing a machine-learning framework. Given the specifications of a finite-state machine A and its circuit implementation B, the goal of CC is to verify the correctness of B. Conformance checking is a hard problem; typically, various formal methods, simulation techniques, and meta-heuristics are employed to resolve it. However, even for moderate-size FSMs, these approaches either become computationally unmanageable or are unable to provide adequate error coverage. In this work, we train a deep neural network (DNN) with a fraction of the I/O transitions of machine A. Following the training phase, the DNN is validated with the remaining I/O pairs. Next, given an input, its predicted output is compared with the one that is observed from its circuit implementation B, and prediction-accuracy is recorded. In order to check the effectiveness of the scheme, various design errors, modeled by output- and transfer-type faults, have been injected in B to derive mutant circuits. Experiments show improvements with respect to CPU-time and error-coverage compared to earlier approaches reported in the literature. In the second part of the work, we adopt a technique for modifying circuit B by adding extra hardware so that the augmented machine becomes easily verifiable while preserving the original functionalities. The proposed modification, however, does not insert any scan-chain, and thus, it is not vulnerable to scan-based security threats. When DNN-aided experiments are performed on the modified machines, the parameters such as CPU-time or error coverage show improvements significantly. Experiments performed on MCNC and ISCAS-89 FSM-benchmarks demonstrate the efficacy of the proposed method.