Abstract
Early availability of estimated values of critical Power-Performance-Area [PPA] parameters which are known only after end of EDA tool run, can be of immense value in accelerating design convergence effort in complex SOC designs. Long tool runtime acts as bottleneck for design turn-around-time as well as engineering productivity. AI/ML can be a game changer in this direction with high potential of predicting these key parameters before/parallel to actual tool-based runs once trained on a rich dataset. An early work is demonstrated in physical synthesis domain using supervised Machine Learning where a model can predict relevant PPA component data such as Timing slack, Critical Path Depth, Leakage Power, Area among others within 6-10% typical accuracy. This study is based on sub10nm SOC design implementation dataset operating at typical clock speed of 1 GHz.