Misfit stress in p/p+ epitaxial silicon wafers: effect and elimination

W. Lin; D.W. Hill; C.L. Paulnack; M.J. Kelly

doi:10.1109/VTSA.1991.246712

1991 International Symposium on VLSI Technology, Systems, and Applications

Misfit stress in p/p+ epitaxial silicon wafers: effect and elimination

Year: 1991, Pages: 57,58,59,60

DOI Bookmark: 10.1109/VTSA.1991.246712

Authors

W. Lin, AT&T Bell Labs., Allentown, PA, USA
D.W. Hill, AT&T Bell Labs., Allentown, PA, USA
C.L. Paulnack, AT&T Bell Labs., Allentown, PA, USA
M.J. Kelly, AT&T Bell Labs., Allentown, PA, USA

Abstract

A large lattice mismatch occurs when lightly boron doped (E15 cm/sup -3/) epitaxial silicon layers are deposited on a heavily boron doped (E19 cm/sup -3/) substrate. The misfit stress causes wafer bow and the formation of misfit dislocations at the interface. The structure of misfit dislocation and effect of misfit stress on p/p+ wafer processing are discussed. A method for elimination of the misfit stress in p/p+ silicon wafers via lattice compensation is presented.<>

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Misfit stress in p/p+ epitaxial silicon wafers: effect and elimination

Authors

Abstract

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