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2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

Oct. 19 2022 to Oct. 21 2022

Austin, TX, USA

ISBN: 978-1-6654-5938-9

Table of Contents

Title PageFreely available from IEEE.pp. i-i
Copyright PageFreely available from IEEE.pp. i-i
ForewordFreely available from IEEE.pp. i-ii
CommitteesFreely available from IEEE.pp. i-v
Awards PageFreely available from IEEE.pp. i-ii
Image Degradation due to Interacting Adjacent Hot PixelsFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Glenn H. Chapman, Klinsmann J. Coelho Silva Meneses, Israel Koren, Zahava Koren
Understanding time-varying vulnerability accross GPU Program LifetimeFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Hao Qiu, Semiu A. Olowogemo, Bor-Tyng Lin, William H. Robinson, Daniel B. Limbrick
SET Hardened Derivatives of QDI Buffer TemplateFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Zaheer Tabassam, Andreas Steininger
Toward the hardening of real-time operating systemsFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Alberto Bosio, Stefano Di Carlo, Maurizio Rebaudengo, Alessandro Savino
Is RISC-V ready for Space? A Security PerspectiveFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Luca Cassano, Stefano Di Mascio, Alessandro Palumbo, Alessandra Menicucci, Gianluca Furano, Giuseppe Bianchi, Marco Ottavi
Neutron Irradiation Testing and Analysis of a Fault-Tolerant RISC-V System-on-ChipFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Douglas A. Santos, André M. P. Mattos, Lucas M. Luza, Carlo Cazzaniga, Maria Kastriotou, Douglas R. Melo, Luigi Dilillo
CRLock: A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer LevelFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Masayoshi Yoshimura, Atsuya Tsujikawa, Hiroshi Yamazaki, Toshinori Hosokawa
Preventing Soft Errors and Hardware Trojans in RISC-V CoresFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Edian B. Annink, Gerard Rauwerda, Edwin Hakkennes, Alessandra Menicucci, Stefano Di Mascio, Gianluca Furano, Marco Ottavi
Evaluation of Hiding-based Countermeasures against Deep Learning Side Channel Attacks with Pre-trained NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Kostas Nomikos, Athanasios Papadimitriou, Mihalis Psarakis, Aggelos Pikrakis, Vincent Beroulle
Analysis of Proton-induced Single Event Effect in the On-Chip Memory of Embedded ProcessFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Corrado De Sio, Sarah Azimi, Luca Sterpone, David Merodio Codinachs
INTERPLAY: An Intelligent Model for Predicting Performance Degradation due to Multi-cache Way-disablingFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Panagiota Nikolaou, Yiannakis Sazeides, Maria K. Michael
HPMA-NTRU: High-Performance Polynomial Multiplication Accelerator for NTRUFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Pengzhou He, Yazheng Tu, Ayesha Khalid, Máire O’Neill, Jiafeng Xie
Integral Sampler and Polynomial Multiplication Architecture for Lattice-based CryptographyFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Antian Wang, Weihang Tan, Keshab K. Parhi, Yingjie Lao
Efficient Loop Abort Fault Attacks on Supersingular Isogeny based Key Exchange (SIKE)Full-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Piyush Beegala, Debapriya Basu Roy, Prasanna Ravi, Shivam Bhasin, Anupam Chattopadhyay, Debdeep Mukhopadhyay
Online scheduling of concurrent Memory BISTs execution at Real-Time Operating-System levelFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Francesco Angione, Paolo Bernardi, Gabriele Filipponi, Claudia Tempesta, Matteo Sonza Reorda, Davide Appello, Vincenzo Tancorre, Roberto Ugioli
Cross-Correlation Approach to Detecting Issue Test Sites in Massive Parallel TestingFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
Storage-Based Logic Built-In Self-Test with Variable-Length Test DataFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Irith Pomeranz
Model-Based Analysis of Single-Event Upset (SEU) Vulnerability of 6T SRAM Using FinFET TechnologiesFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
by Semiu A. Olowogemo, Hao Qiu, Bor-Tyng Lin, William H. Robinson, Daniel B. Limbrick
Aging Effects On Clock Gated Memory Phase PathsFull-text access may be available. Sign in or learn about subscription options.pp. 1-5
by Amlan Ghosh, Saroj Satapathy, Jaydeep P. Kulkarni, Prashant D. Joshi
Study and Comparison of QDI Pipeline Components’ Sensitivity to Permanent FaultsFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Raghda El Shehaby, Andreas Steininger
MetaFS: Model-driven Fault Simulation FrameworkFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
by Endri Kaja, Nicolas Gerlin, Monideep Bora, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker
X-Ray Fault Injection: Reviewing Defensive Approaches from a Security PerspectiveFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
by Nasr-Eddine Ouldei Tebina, Nacer-Eddine Zergainoh, Paolo Maistri
Operational Age Estimation of ICs using Gaussian Process RegressionFull-text access may be available. Sign in or learn about subscription options.pp. 1-5
by Anmol Singh Narwariya, Pabitra Das, Saqib Khursheed, Amit Acharyya
Thread-level Parallelism in Fault Simulation of Deep Neural Networks on Multi-Processor SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
by Masoomeh Karami, Mohammad-Hashem Haghbayan, Masoumeh Ebrahimi, Antonio Miele, Juha Plosila
Improving DNN Fault Tolerance in Semantic Segmentation ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Stéphane BurelT, Adrian EvansT, Lorena Anghel
Selective Hardening of CNNs based on Layer Vulnerability EstimationFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Cristiana Bolchini, Luca Cassano, Antonio Miele, Alessandro Nazzari
Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input VoltagesFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Jianan Wen, Andrea Baroni, Eduardo Perez, Markus Ulbricht, Christian Wenger, Milos Krstic
Evaluation of the Effects of SEUs on Configuration Memories in FPGA Implemented QC-LDPC DecodersFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Zhen Gao, Yinghao Cheng, Pedro Reviriego
RADPlace-MS: A Timing-Driven Placer and Optimiser for ASICs Radiation HardeningFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Christos Georgakidis, Stavros Simoglou, Christos Sotiriou
A Polarity-Driven Radiation-Hardened Latch design for Single Event Upset ToleranceFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Shanshan Liu, Guo Jing, Xiaochen Tang, Pedro Reviriego, Fabrizio Lombardi
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