Important Dates
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- Submission Deadline: 1 March 2024
Publication: December 2024
Authors are invited to submit a manuscript to the special section on Emerging In-Memory Computing Architectures and Applications. As the journal’s accent is on “Emerging Computing”, all submissions should fall in the domain of interest of the journal. Relevant topics of interest to this special section include (but are not limited to):
- Emerging In-Memory Computing based systems: architectures, design methodologies and framework, circuits, device modeling;
- Emerging logic and circuit design concepts using memory devices: threshold logic, stateful logic, multi-level logic;
- Test and Reliability for In-Memory Computing circuits and systems: defect, fault modeling, test generation, DfT and Fault tolerance techniques applied to IMC circuits and systems.
- Security for In-Memory Computing systems and In-Memory Computing paradigm for security: threats, attacks and countermeasures for IMC, exploiting IMC paradigm to enhance the security of a computing system;
- Emerging paradigms for In-Memory Computation programming: code generation and optimization, programming models;
- Real World Applications of In-Memory Computation.
Submission Guidelines
The papers submitted to this special section must include new significant technical contributions that fall within the scope of the journal. Contributions describing an overall working system and reporting real world deployment experiences are particularly of interest. The submissions must include clear evaluations of the proposed solutions (based on simulation and/or implementations results) and comparisons with state-of-the-art solutions.
For additional information please contact the Guest Editors by sending an email to tetc.ss.imc.2023@gmail.com . Papers under review elsewhere are not acceptable for submission. Extended versions of published conference papers (to be included as part of the submission together with a summary of differences) are welcome, but there must have at least 40% of new impacting technical/scientific material in the submitted journal version and there should be less than 50% verbatim similarity level as reported by a tool (such as CrossRef).
Guidelines concerning the submission process, LaTeX and Word templates can be found here.
While submitting through ScholarOne, at please select the option ” Special Section on Emerging In-Memory Computing Architectures and Applications.”
As per TETC policies, only full-length papers (10-16 pages with technical material, double column – papers beyond 12 pages will be subject to MOPC, as per CS policies -) can be submitted to special sections. The bibliography should not exceed 45 items and each Author’s bio should not exceed 150 words.
- Alberto Bosio, Ecole Centrale de Lyon – Institute of Nanotechnology, France (IEEE Member)
- Nima Taherinejad, Institute of Computer Engineering, Heidelberg University, Heidelberg, Germany (IEEE Member)
- Deliang Fan, Johns Hopkins University, Baltimore, MD, USA (IEEE Member)
